LOCAL RESOURCES or INDEX - contains the main entries into the environment : lectures, readings, models, language aspects, design methods, tools, .. INDEX provides the access to VHDL analyzer and Quiz

[ LECTURES | READINGS | ASPECTS | TOOLS | METHODS | MODELS | ANALYZER | QUIZ ] 

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USER INTERFACE contains the communication windows with the given type of user: student, designer, guest, ..

• news concerning VHDLand VCL
• teacher and student  windows for an interactive chat
• exercices given by the teacher
• project proposed by the teacher or designer
• participants of the lecture/course

• WWW search allowing direct access to WEB-wide search engines
• official organizations with activities related to VHDL
• WEB based tutorials on VHDL
• available model libraries and VHDL cores
• links to VHDL related standard descriptions
• VHDL related conferences
• available services concerning VHDL use
• VHDL related tools available via Internet

• your first lesson
• part 1 : VHDL basics
• part 2 : VHDL standard modeling techniques, synthesis and reuse
• part 3 : VHDL extensions

This section contains the foils prepared for the VHDL lectures. These foils may be used with an overhead projector with a minimal resolution of 600*400 pixels.  The foils are organized to provide a support material for at least 20 hours of lecture.
The lectures are organized along the following themes:

PART I: Language and Modeling

• Introduction to HDLs history, standardization process and applications
• VHDL basic elements
• Functional descriptions
• Time representation
• Structural descriptions
• Complex descriptions

• Modeling combinational circuits
• Modeling sequential circuits
• Modeling FSMs
• Modeling arithmetical circuits
• Modeling processors

• Standard modeling techniques
• Virtual components
• Virtual sockets
• Modeling for reusability
• Designing with reuse

• behavior description :
• VHDL offers a wide spectrum of mechanisms which allow the designer to describe the functions and the behavior of the circuits and systems
• structure description :
• VHDL provides hierarchically structured descriptions based on the notion of entities and components and their interconnections
• time description :
• VHDL introduces the simulation time required to describe the behavior of the circuits and systems according the temporal axis

• analyzers - compilers
• simulators (dynamic and static timing analysis)
• synthesizers

• compilation
• simulation (dynamic and static timing analysis)
• synthesis
• block/core based design

• VHDL as a normal sequential programming language - programmer point of view.
• VHDL as circuit design tool providing the facilities for describing the modular and hierarchical structure - circuit designer point of view.
• VHDL integrates the programming language features with a discrete event timing model to allow simulation of behavior - simulation semantics.
• VHDL combines the behavioral and structural description in order to design and simulate the model of systems - system designer point of view.
• VHDL for modeling complex systems such as microprocessors - architecture designers.
• VHDL and synthesis: synthetizable VHDL and synthetizable VHDL descriptions - circuit designer point of view.
• VHDL'93 provides the extensions for system level descriptions - system designer point of view.
• VHDL and standard modeling techniques for ASIC circuits based on VITAL initiative - ASIC modelers and designers.
• VHDL based tools - modeling, simulation, synthesis.

• ATM switches - These entry provides some examples of VHDL models used to synthesis of ATM switches
• real time systems (in french) - These pages illustrate the use of VHDL and VHDL simulation environment for the modeling and evaluation of basic real-time systems.
• processors (in french) - These pages illustrate how to use VHDL to model and to synthesize DSP processors
• floating point unit  - These pages show the modeling of 32/40-bit floating point unit of modern DSP processor
• FPGA based synthesis - These example illustrates the use of VHDL as design entry to Field-Programmable Gate Array based implementation of a multisensor receiver architecture
• and many others in ASCII form

Independently, at each place and instance you can refer to the prepared links and surf over the available material.

The external links below, are related to the accessible URLs including the presentation of:

Organizations

• VIUF Internet Services (VHDL International Users Forum)
• OVI - Open Verilog International

• ISD - Integrated Systems Design Magazine
• Virtual Chip Design
• Design and Test

• VHDL UK - books

• Kevin Shahill - VHDL for Programmable Logic

• VHDL-Database (Strasbourg - France)
• VHDL models (logic_circuits, processors,.. )
• VAutomation - synthetisable cores
• CAST - cores and models for VHDL design
• LIBRARY TECHNOLOGIES - ASIC libraries
• Artisan Components
• Western Design Center - licensable cores and modules

• VHDL related standards (IEEE - std_logic_1164, VITAL, ..)
• VSI Alliance - virtual components and interface standards (Virtual Socket Interface) VSI Alliance
• analog extensions to VHDL (AMS)
• VHDL synthesis standards

• modeling taxonomy
• VHDL coding guidelines (courses, tutorials, ..)
• VHDL reference materials and publications (books - VHDL Cookbook, VHDL Standard Report, .. )

• VHDL tutorial - Erlangen (german version)
• VHDL tutorial (prepared by Zainalabedin Navabi)
• VITAL tutorial
• VHDL Synthesis Tutorial - (by Bob Reese - Missisipi State University)
• Hamburg VHDL Archive
• VHDL -UK - communication network

Professional

Simulators

• ModelTech: ModelTech simulator
• Leapfrog: Leapfrog VHDL simulator
• VeriBest:
• ViewLogic:
Generators
• Menthor: Menthor Graphics Renoir
• SUMMIT - Visual HDL for VHDL
• Speed: Speed chart
• Translogic : The graphical System Design Tool (uk)
• generating VHDL from i-Logix (university Manitoba)
Synthesizers
• Synopsis : COSSAP, Design Compiler,Behavioral Compiler
• Xilinx: an FPGA company
• Altera : an FPGA company
• Cypress : an FPGA/ASIC company
Translators
• Alternative System Concepts - V2V demo: VHDL <-> Verilog translators
• XILINX: conversion lca to vhdl
• tool: VHDL Object Model
Verification tools
• VHDL verification tools
Others
• Veritools home page (Verilog)

Public Domain

pretty printing:
• mvp_v11 (69K compressed tar)
• The pretty printer of Michael Knieser: vhdl-nice (version 0.1c?)
• A vhdl to HTML converter by Michael Knieser: vhdl2html
VHDL grammar and parsing:
• VHDL-93 BNF description
• University of Dortmund VAUL parser and frontend:

 

VAUL home page (University of Dortmund)
local copy (University of Hamburg) (520K compressed tar. Needs GNU compiler). The complete Vhdl Analyzer and Utility Library (VAUL) with flex/bison/C++ based parser.

• A VHDL-93 compliant parser written in SWI-Prolog with (experimental) VHDL-93 design description browser:

 

VHDL-93 parser (gziped tar archive),
Readme

• uc_vhdlgrammar (lex yacc) (20K compressed ASCII)
• VHDLParser and VHDLTree A GNU licensed VHDL parser and parse-tree viewer written in Java!
• Thomas Dettmers VHDL parser vhdl-lexyacc.1.4 (lex yacc)(19K compressed tar)
• University of Twente VHDL parser vhdl-rexlalr.1.2 (35K compressed tar. Needs the GMD Compiler Tool Box CCTB)
• University of Twente VHDL parser frontend vhdlfront.1.1(100K compressed tar)
• VHDL Object Model Parser (36K compressed tar) (written in the REFINE system, Ohio Board of Regents and the University of Cincinnati).

 

individual files

Other tools:
• A BLIF -> VHDL converter: blif2vhdl 51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included.
• A prototype VHDL-2-C compiler (for sequential statements): vhdl-2-c
• A FSM-schematic to VHDL code generator, with C sources: (takes xfig drawings of FSMs and generates synthesizable VHDL code, the MSC thesis of Thomas C. Mayo) (2.5K README) v 2.4 (240K tar archive) v 2.0 (65K .tar.Z archive)

(205K documentation)
• The Alliance CAD system (sources) includes the only free VHDL simulator (more or less ?) ; it can be ftp'd from
• ftp.ibm.fr [132.227.60.2] in /ibp/softs/masi/alliance
• ftp-masi.ibp.fr [132.227.64.26] in /pub/cao-vlsi/alliance
• cao-vlsi.ibp.fr [132.227.60.20] in /pub/alliance

• OVI - Open Verilog International
• DAI - Verilog Analysis Tools
• Fintronic - mixed event and cycle driven Verilog simulators