netlist code

VHDL implementation of a multisensor receiver

prepared by P. Bakowski

This listing provides the netlist generated from VHDL description of a multisensor receiver by ASIC/FPGA synthetizer

#cell2 * lms_final lg * 1 any 0 v9r1.0
# "19-Jun-97 GMT" "7:38:47 GMT" "19-Jun-97 GMT" "7:38:47 GMT" scrand * .
# AsicSynOPEN [vhd]lms_final
# AsicSynSYNTHESIZE
#####################################################################
# A R E A R E P O R T #
#####################################################################
# cell "LMS_FINAL_P" #
#===================================================================#
Num Gate Eqv Tot Gate Basecount Total
Cell Name Insts Per Cell Equivs Per Cell Basecount
--------- ----- -------- -------- -------- --------
add_6_p 1 146.0 146.0 8.76 8.76
..lms_final_p 1 3315.0 3315.0 136.07 136.07
mult_4_p 1 1767.0 1767.0 106.12 106.12
mult_7_p 2 767.0 1534.0 46.08 92.16
sub_3_p 1 147.0 147.0 8.82 8.82
sub_8_p 1 147.0 147.0 8.82 8.82
Totals: 7 7056.0 360.75
Total pins: 620
Total nets: 310
Average pins per net: 2.0; Max pins per net: 2
(excluding power and ground nets)
# AsicSynQUIT