VHDL essentials

code

VHDL implementation of a multisensor receiver for DS-CDMA applications

prepared by P. Bakowski

This synthetisable description is composed from several entities to be synthetised separately.

-- Version finale du LMS (teste sur maquette)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

USE COMPASS_LIB.COMPASS_arith.ALL;

entity sub_3 is

port(sub_e1:in signed_vector(11 downto 0);

sub_e2:in signed_vector(11 downto 0);

sub_s1:out signed_vector(11 downto 0));

end sub_3;

architecture behavior of sub_3 is

begin

process(sub_e1,sub_e2)

variable a: signed_vector(11 downto 0);

begin

a:=sign_extend(sub_e1,12)-sign_extend(sub_e2,12);

sub_s1<=a;

end process;

end behavior;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

USE COMPASS_LIB.COMPASS_arith.ALL;

entity mult_4 is

port(mult_e1:in signed_vector(11 downto 0);

mult_e2:in signed_vector(11 downto 0);

mult_s1:out signed_vector(11 downto 0));

end mult_4;

architecture behavior of mult_4 is

begin

process(mult_e1,mult_e2)

variable a: signed_vector(23 downto 0);

begin

a:=mult_e1*mult_e2;

mult_s1(11 downto 11)<=a(23 downto 23);

mult_s1(10 downto 10)<=a(19 downto 19);

mult_s1(9 downto 0)<=a(18 downto 9);

end process;

end behavior;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

USE COMPASS_LIB.COMPASS_arith.ALL;

entity add_6 is

port(add_e1:in signed_vector(11 downto 0);

add_e2:in signed_vector(11 downto 0);

add_s1:out signed_vector(11 downto 0));

end add_6;

architecture behavior of add_6 is

begin

process(add_e1,add_e2)

variable a: signed_vector(11 downto 0);

begin

a:=sign_extend(add_e1,12)+sign_extend(add_e2,12);

add_s1<=a;

end process;

end behavior;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

USE COMPASS_LIB.COMPASS_arith.ALL;

entity mult_7 is

port(mult_e1:in signed_vector(7 downto 0);

mult_e2:in signed_vector(7 downto 0);

mult_s1:out signed_vector(11 downto 0));

end mult_7;

architecture behavior of mult_7 is

begin

process(mult_e1,mult_e2)

variable a: signed_vector(15 downto 0);

begin

a:=mult_e1*mult_e2;

mult_s1(11 downto 11)<=a(15 downto 15);

mult_s1(10 downto 8)<=a(14 downto 12);

mult_s1(7 downto 0)<=a(11 downto 4);

end process;

end behavior;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

USE COMPASS_LIB.COMPASS_arith.ALL;

entity sub_8 is

port(sub_e1:in signed_vector(11 downto 0);

sub_e2:in signed_vector(11 downto 0);

sub_s1:out signed_vector(11 downto 0));

end sub_8;

architecture behavior of sub_8 is

begin

process(sub_e1,sub_e2)

variable a: signed_vector(11 downto 0);

begin

a:=sign_extend(sub_e1,12)-sign_extend(sub_e2,12);

sub_s1<=a;

end process;

end behavior;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

USE COMPASS_LIB.COMPASS_ARITH.ALL;

entity e_lms_final is

port(reset:in std_logic_vector(0 downto 0);

clk:in std_logic;

sortie_1: out signed_vector(11 downto 0);

sortie_2: out signed_vector(11 downto 0);

sortie_3: out signed_vector(11 downto 0);

sortie_4: out signed_vector(11 downto 0);

entree_1: in signed_vector(7 downto 0);

entree_2: in signed_vector(7 downto 0);

entree_3: in signed_vector(7 downto 0);

entree_4: in signed_vector(7 downto 0);

entree_5: in signed_vector(7 downto 0);

entree_6: in signed_vector(7 downto 0);

entree_7: in signed_vector(11 downto 0);

sub3_e1_1: out signed_vector(11 downto 0);

sub3_e1_2: out signed_vector(11 downto 0);

sub3_s1_1: in signed_vector(11 downto 0);

mult4_e1_1: out signed_vector(11 downto 0);

mult4_e1_2: out signed_vector(11 downto 0);

mult4_s1_1: in signed_vector(11 downto 0);

add6_e1_1: out signed_vector(11 downto 0);

add6_e1_2: out signed_vector(11 downto 0);

add6_s1_1: in signed_vector(11 downto 0);

mult7_e1_1: out signed_vector(7 downto 0);

mult7_e1_2: out signed_vector(7 downto 0);

mult7_s1_1: in signed_vector(11 downto 0);

mult7_e2_1: out signed_vector(7 downto 0);

mult7_e2_2: out signed_vector(7 downto 0);

mult7_s2_1: in signed_vector(11 downto 0);

sub8_e1_1: out signed_vector(11 downto 0);

sub8_e1_2: out signed_vector(11 downto 0);

sub8_s1_1: in signed_vector(11 downto 0));

end e_lms_final;

Architecture behavior of e_lms_final is

signal c_step:integer range 0 to 4;

signal dly5_s: signed_vector(11 downto 0);

signal dly7_s: signed_vector(11 downto 0);

signal dly9_s: signed_vector(11 downto 0);

signal dly11_s: signed_vector(11 downto 0);

signal dly13_s: signed_vector(11 downto 0);

signal dly15_s: signed_vector(11 downto 0);

signal dly17_s: signed_vector(11 downto 0);

signal dly20_s: signed_vector(11 downto 0);

signal dly22_s: signed_vector(11 downto 0);

signal dly25_s: signed_vector(11 downto 0);

signal dly37_s: signed_vector(11 downto 0);

signal dly39_s: signed_vector(11 downto 0);

signal dly41_s: signed_vector(11 downto 0);

signal dly43_s: signed_vector(11 downto 0);

signal dly45_s: signed_vector(11 downto 0);

signal dly46_s: signed_vector(11 downto 0);

signal dly47_s: signed_vector(11 downto 0);

signal dly49_s: signed_vector(11 downto 0);

signal dly50_s: signed_vector(11 downto 0);

signal dly51_s: signed_vector(11 downto 0);

Begin

process(reset,clk)

begin

if reset="1" then

c_step<=0;

sortie_1<= extend("0",12);

sortie_2<= extend("0",12);

sortie_3<= extend("0",12);

sortie_4<= extend("0",12);

dly5_s<=extend("0",12);

dly7_s<=extend("0",12);

dly9_s<=extend("0",12);

dly11_s<="000000000000";

dly13_s<=extend("0",12);

dly15_s<=extend("0",12);

dly17_s<=extend("0",12);

dly20_s<=extend("0",12);

dly22_s<=extend("0",12);

dly25_s<=extend("0",12);

dly37_s<=extend("0",12);

dly39_s<=extend("0",12);

dly41_s<=extend("0",12);

dly43_s<=extend("0",12);

dly45_s<=extend("0",12);

dly46_s<=extend("0",12);

dly47_s<=extend("0",12);

dly49_s<=extend("0",12);

dly50_s<=extend("0",12);

dly51_s<=extend("0",12);

elsif rising_edge(clk) then

CASE c_step is

WHEN 0 =>

sortie_1(11 downto 0) <= dly11_s(11 downto 0);

sortie_2(11 downto 0) <= dly9_s(11 downto 0);

sortie_3(11 downto 0) <= dly7_s(11 downto 0);

sortie_4(11 downto 0) <= dly5_s(11 downto 0);

sub3_e1_1(11 downto 0) <= dly5_s(11 downto 0);

sub3_e1_2(11 downto 0) <= dly13_s(11 downto 0);

mult4_e1_1(11 downto 0) <= entree_7(11 downto 0);

mult4_e1_2(11 downto 0) <= dly49_s(11 downto 0);

add6_e1_2(11 downto 0) <= dly17_s(11 downto 0);

add6_e1_1(11 downto 0) <= dly20_s(11 downto 0);

mult7_e1_2(7 downto 0) <= entree_3(7 downto 0);

mult7_e1_1(7 downto 0) <= entree_5(7 downto 0);

mult7_e2_2(7 downto 0) <= entree_4(7 downto 0);

mult7_e2_1(7 downto 0) <= entree_6(7 downto 0);

sub8_e1_1(11 downto 0) <= dly22_s(11 downto 0);

sub8_e1_2(11 downto 0) <= dly25_s(11 downto 0);

c_step <= 1;

WHEN 1 =>

dly5_s(11 downto 0) <= sub3_s1_1(11 downto 0);

sub3_e1_1(11 downto 0) <= dly7_s(11 downto 0);

sub3_e1_2(11 downto 0) <= dly15_s(11 downto 0);

dly13_s(11 downto 0) <= mult4_s1_1(11 downto 0);

mult4_e1_1(11 downto 0) <= entree_7(11 downto 0);

mult4_e1_2(11 downto 0) <= dly50_s(11 downto 0);

dly17_s(11 downto 0) <= mult7_s1_1(11 downto 0);

dly20_s(11 downto 0) <= mult7_s2_1(11 downto 0);

mult7_e1_2(7 downto 0) <= entree_3(7 downto 0);

mult7_e1_1(7 downto 0) <= entree_6(7 downto 0);

mult7_e2_2(7 downto 0) <= entree_4(7 downto 0);

mult7_e2_1(7 downto 0) <= entree_5(7 downto 0);

add6_e1_2(11 downto 0) <= dly41_s(11 downto 0);

add6_e1_1(11 downto 0) <= dly46_s(11 downto 0);

sub8_e1_2(11 downto 0) <= dly43_s(11 downto 0);

sub8_e1_1(11 downto 0) <= dly45_s(11 downto 0);

dly49_s(11 downto 0) <= sub8_s1_1(11 downto 0);

dly50_s(11 downto 0) <= add6_s1_1(11 downto 0);

c_step <= 2;

WHEN 2 =>

dly7_s(11 downto 0) <= sub3_s1_1(11 downto 0);

sub3_e1_1(11 downto 0) <= dly9_s(11 downto 0);

sub3_e1_2(11 downto 0) <= dly37_s(11 downto 0);

dly15_s(11 downto 0) <= mult4_s1_1(11 downto 0);

dly22_s(11 downto 0) <= mult7_s1_1(11 downto 0);

dly25_s(11 downto 0) <= mult7_s2_1(11 downto 0);

mult7_e1_1(7 downto 0) <= entree_5(7 downto 0);

mult7_e1_2(7 downto 0) <= entree_2(7 downto 0);

mult7_e2_1(7 downto 0) <= entree_5(7 downto 0);

mult7_e2_2(7 downto 0) <= entree_1(7 downto 0);

mult4_e1_1(11 downto 0) <= entree_7(11 downto 0);

mult4_e1_2(11 downto 0) <= dly51_s(11 downto 0);

dly51_s(11 downto 0) <= sub8_s1_1(11 downto 0);

c_step <= 3;

WHEN 3 =>

dly47_s(11 downto 0) <= add6_s1_1(11 downto 0);

dly9_s(11 downto 0) <= sub3_s1_1(11 downto 0);

sub3_e1_1(11 downto 0) <= dly11_s(11 downto 0);

sub3_e1_2(11 downto 0) <= dly39_s(11 downto 0);

mult7_e1_1(7 downto 0) <= entree_6(7 downto 0);

mult7_e1_2(7 downto 0) <= entree_1(7 downto 0);

mult7_e2_1(7 downto 0) <= entree_6(7 downto 0);

mult7_e2_2(7 downto 0) <= entree_2(7 downto 0);

dly37_s(11 downto 0) <= mult4_s1_1(11 downto 0);

mult4_e1_2(11 downto 0) <= dly47_s(11 downto 0);

mult4_e1_1(11 downto 0) <= entree_7(11 downto 0);

dly41_s(11 downto 0) <= mult7_s2_1(11 downto 0);

dly43_s(11 downto 0) <= mult7_s1_1(11 downto 0);

c_step <= 4;

WHEN 4 =>

dly11_s(11 downto 0) <= sub3_s1_1(11 downto 0);

dly39_s(11 downto 0) <= mult4_s1_1(11 downto 0);

dly45_s(11 downto 0) <= mult7_s1_1(11 downto 0);

dly46_s(11 downto 0) <= mult7_s2_1(11 downto 0);

c_step <= 0;

END CASE;

end if;

end process;

end behavior;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

USE COMPASS_LIB.STDCOMP.ALL;

entity lms_final is

port(reset:in std_logic_vector(0 downto 0);

clk:in std_logic;

sortie_1: out signed_vector(11 downto 0);

sortie_2: out signed_vector(11 downto 0);

sortie_3: out signed_vector(11 downto 0);

sortie_4: out signed_vector(11 downto 0);

entree_1: in signed_vector(7 downto 0);

entree_2: in signed_vector(7 downto 0);

entree_3: in signed_vector(7 downto 0);

entree_4: in signed_vector(7 downto 0);

entree_5: in signed_vector(7 downto 0);

entree_6: in signed_vector(7 downto 0);

entree_7: in signed_vector(11 downto 0));

end lms_final;

Architecture behavior of lms_final is

signal ireset:std_logic_vector(0 downto 0);

signal iclk:std_logic;

signal Vdd1,Vdd2,Vdd3,Vdd4:std_logic;

signal Vss1,Vss2,Vss3,Vss4:std_logic;

component e_lms_final

port(reset:in std_logic_vector(0 downto 0);

clk:in std_logic;

sortie_1: out signed_vector(11 downto 0);

sortie_2: out signed_vector(11 downto 0);

sortie_3: out signed_vector(11 downto 0);

sortie_4: out signed_vector(11 downto 0);

entree_1: in signed_vector(7 downto 0);

entree_2: in signed_vector(7 downto 0);

entree_3: in signed_vector(7 downto 0);

entree_4: in signed_vector(7 downto 0);

entree_5: in signed_vector(7 downto 0);

entree_6: in signed_vector(7 downto 0);

entree_7: in signed_vector(11 downto 0);

sub3_e1_1: out signed_vector(11 downto 0);

sub3_e1_2: out signed_vector(11 downto 0);

sub3_s1_1: in signed_vector(11 downto 0);

mult4_e1_1: out signed_vector(11 downto 0);

mult4_e1_2: out signed_vector(11 downto 0);

mult4_s1_1: in signed_vector(11 downto 0);

add6_e1_1: out signed_vector(11 downto 0);

add6_e1_2: out signed_vector(11 downto 0);

add6_s1_1: in signed_vector(11 downto 0);

mult7_e1_1: out signed_vector(7 downto 0);

mult7_e1_2: out signed_vector(7 downto 0);

mult7_s1_1: in signed_vector(11 downto 0);

mult7_e2_1: out signed_vector(7 downto 0);

mult7_e2_2: out signed_vector(7 downto 0);

mult7_s2_1: in signed_vector(11 downto 0);

sub8_e1_1: out signed_vector(11 downto 0);

sub8_e1_2: out signed_vector(11 downto 0);

sub8_s1_1: in signed_vector(11 downto 0));

end component;

for all:e_lms_final use entity work.e_lms_final(behavior);

component sub_3

port(sub_e1: in signed_vector(11 downto 0);

sub_e2: in signed_vector(11 downto 0);

sub_s1: out signed_vector(11 downto 0));

end component;

for all:sub_3 use entity work.sub_3(behavior);

component mult_4

port(mult_e1: in signed_vector(11 downto 0);

mult_e2: in signed_vector(11 downto 0);

mult_s1: out signed_vector(11 downto 0));

end component;

for all:mult_4 use entity work.mult_4(behavior);

component add_6

port(add_e1: in signed_vector(11 downto 0);

add_e2: in signed_vector(11 downto 0);

add_s1: out signed_vector(11 downto 0));

end component;

for all:add_6 use entity work.add_6(behavior);

component mult_7

port(mult_e1: in signed_vector(7 downto 0);

mult_e2: in signed_vector(7 downto 0);

mult_s1: out signed_vector(11 downto 0));

end component;

for all:mult_7 use entity work.mult_7(behavior);

component sub_8

port(sub_e1: in signed_vector(11 downto 0);

sub_e2: in signed_vector(11 downto 0);

sub_s1: out signed_vector(11 downto 0));

end component;

for all:sub_8 use entity work.sub_8(behavior);

signal isortie_1: signed_vector(11 downto 0);

signal isortie_2: signed_vector(11 downto 0);

signal isortie_3: signed_vector(11 downto 0);

signal isortie_4: signed_vector(11 downto 0);

signal ientree_1: signed_vector(7 downto 0);

signal ientree_2: signed_vector(7 downto 0);

signal ientree_3: signed_vector(7 downto 0);

signal ientree_4: signed_vector(7 downto 0);

signal ientree_5: signed_vector(7 downto 0);

signal ientree_6: signed_vector(7 downto 0);

signal ientree_7: signed_vector(11 downto 0);

signal isub3_e1_1: signed_vector(11 downto 0);

signal isub3_e1_2: signed_vector(11 downto 0);

signal isub3_s1_1: signed_vector(11 downto 0);

signal imult4_e1_1: signed_vector(11 downto 0);

signal imult4_e1_2: signed_vector(11 downto 0);

signal imult4_s1_1: signed_vector(11 downto 0);

signal iadd6_e1_1: signed_vector(11 downto 0);

signal iadd6_e1_2: signed_vector(11 downto 0);

signal iadd6_s1_1: signed_vector(11 downto 0);

signal imult7_e1_1: signed_vector(7 downto 0);

signal imult7_e1_2: signed_vector(7 downto 0);

signal imult7_s1_1: signed_vector(11 downto 0);

signal imult7_e2_1: signed_vector(7 downto 0);

signal imult7_e2_2: signed_vector(7 downto 0);

signal imult7_s2_1: signed_vector(11 downto 0);

signal isub8_e1_1: signed_vector(11 downto 0);

signal isub8_e1_2: signed_vector(11 downto 0);

signal isub8_s1_1: signed_vector(11 downto 0);

begin

process(reset,clk,isortie_1,isortie_2,isortie_3,isortie_4,entree_1,entree_2,entree_3,entree_4,entree_5,entree_6,entree_7)

begin

ireset<=reset;

iclk<=clk;

sortie_1<=isortie_1;

sortie_2<=isortie_2;

sortie_3<=isortie_3;

sortie_4<=isortie_4;

ientree_1<=entree_1;

ientree_2<=entree_2;

ientree_3<=entree_3;

ientree_4<=entree_4;

ientree_5<=entree_5;

ientree_6<=entree_6;

ientree_7<=entree_7;

end process;

i1_e_lms_final: e_lms_final

port map (reset=>ireset,clk=>iclk,

sortie_1=>isortie_1,

sortie_2=>isortie_2,

sortie_3=>isortie_3,

sortie_4=>isortie_4,

entree_1=>ientree_1,

entree_2=>ientree_2,

entree_3=>ientree_3,

entree_4=>ientree_4,

entree_5=>ientree_5,

entree_6=>ientree_6,

entree_7=>ientree_7,

sub3_e1_1=>isub3_e1_1,

sub3_e1_2=>isub3_e1_2,

sub3_s1_1=>isub3_s1_1,

mult4_e1_1=>imult4_e1_1,

mult4_e1_2=>imult4_e1_2,

mult4_s1_1=>imult4_s1_1,

add6_e1_1=>iadd6_e1_1,

add6_e1_2=>iadd6_e1_2,

add6_s1_1=>iadd6_s1_1,

mult7_e1_1=>imult7_e1_1,

mult7_e1_2=>imult7_e1_2,

mult7_s1_1=>imult7_s1_1,

mult7_e2_1=>imult7_e2_1,

mult7_e2_2=>imult7_e2_2,

mult7_s2_1=>imult7_s2_1,

sub8_e1_1=>isub8_e1_1,

sub8_e1_2=>isub8_e1_2,

sub8_s1_1=>isub8_s1_1);

i1_sub_3: sub_3

port map(sub_e1=>isub3_e1_1,

sub_e2=>isub3_e1_2,

sub_s1=>isub3_s1_1);

i1_mult_4: mult_4

port map(mult_e1=>imult4_e1_1,

mult_e2=>imult4_e1_2,

mult_s1=>imult4_s1_1);

i1_add_6: add_6

port map(add_e1=>iadd6_e1_1,

add_e2=>iadd6_e1_2,

add_s1=>iadd6_s1_1);

i1_mult_7: mult_7

port map(mult_e1=>imult7_e1_1,

mult_e2=>imult7_e1_2,

mult_s1=>imult7_s1_1);

i2_mult_7: mult_7

port map(mult_e1=>imult7_e2_1,

mult_e2=>imult7_e2_2,

mult_s1=>imult7_s2_1);

i1_sub_8: sub_8

port map(sub_e1=>isub8_e1_1,

sub_e2=>isub8_e1_2,

sub_s1=>isub8_s1_1);

end behavior;