// sram.v

// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.

`timescale 1 ps / 1 ps
module sram (
		input  wire        clk,          //     clock.clk
		input  wire        reset,        //     reset.reset
		input  wire        chipselect_n, //  cpu_ctrl.chipselect_n
		input  wire        read_n,       //          .read_n
		input  wire        write_n,      //          .write_n
		input  wire [1:0]  byteenable_n, //          .byteenable_n
		output wire [15:0] readdata,     //          .readdata
		input  wire [15:0] writedata,    //          .writedata
		input  wire [17:0] address,      //          .address
		output wire        sram_ce_n,    // ctrl_sram.export
		output wire        sram_lb_n,    //          .export
		output wire        sram_oe_n,    //          .export
		output wire        sram_ub_n,    //          .export
		output wire        sram_we_n,    //          .export
		inout  wire [15:0] sram_dq,      //          .export
		output wire [17:0] sram_addr     //          .export
	);

	dlk_avalon_sram sram (
		.clk          (clk),          //     clock.clk
		.reset        (reset),        //     reset.reset
		.chipselect_n (chipselect_n), //  cpu_ctrl.chipselect_n
		.read_n       (read_n),       //          .read_n
		.write_n      (write_n),      //          .write_n
		.byteenable_n (byteenable_n), //          .byteenable_n
		.readdata     (readdata),     //          .readdata
		.writedata    (writedata),    //          .writedata
		.address      (address),      //          .address
		.sram_ce_n    (sram_ce_n),    // ctrl_sram.export
		.sram_lb_n    (sram_lb_n),    //          .export
		.sram_oe_n    (sram_oe_n),    //          .export
		.sram_ub_n    (sram_ub_n),    //          .export
		.sram_we_n    (sram_we_n),    //          .export
		.sram_dq      (sram_dq),      //          .export
		.sram_addr    (sram_addr)     //          .export
	);

endmodule
