//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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//use of Altera Corporation's design tools, logic functions and other
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//output files any of the foregoing (including device programming or
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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module btn_s1_arbitrator (
                           // inputs:
                            btn_s1_irq,
                            btn_s1_readdata,
                            clk,
                            cpu_data_master_address_to_slave,
                            cpu_data_master_latency_counter,
                            cpu_data_master_read,
                            cpu_data_master_read_data_valid_sdram_s1_shift_register,
                            cpu_data_master_write,
                            cpu_data_master_writedata,
                            reset_n,

                           // outputs:
                            btn_s1_address,
                            btn_s1_chipselect,
                            btn_s1_irq_from_sa,
                            btn_s1_readdata_from_sa,
                            btn_s1_reset_n,
                            btn_s1_write_n,
                            btn_s1_writedata,
                            cpu_data_master_granted_btn_s1,
                            cpu_data_master_qualified_request_btn_s1,
                            cpu_data_master_read_data_valid_btn_s1,
                            cpu_data_master_requests_btn_s1,
                            d1_btn_s1_end_xfer
                         )
;

  output  [  1: 0] btn_s1_address;
  output           btn_s1_chipselect;
  output           btn_s1_irq_from_sa;
  output  [ 31: 0] btn_s1_readdata_from_sa;
  output           btn_s1_reset_n;
  output           btn_s1_write_n;
  output  [ 31: 0] btn_s1_writedata;
  output           cpu_data_master_granted_btn_s1;
  output           cpu_data_master_qualified_request_btn_s1;
  output           cpu_data_master_read_data_valid_btn_s1;
  output           cpu_data_master_requests_btn_s1;
  output           d1_btn_s1_end_xfer;
  input            btn_s1_irq;
  input   [ 31: 0] btn_s1_readdata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] btn_s1_address;
  wire             btn_s1_allgrants;
  wire             btn_s1_allow_new_arb_cycle;
  wire             btn_s1_any_bursting_master_saved_grant;
  wire             btn_s1_any_continuerequest;
  wire             btn_s1_arb_counter_enable;
  reg     [  1: 0] btn_s1_arb_share_counter;
  wire    [  1: 0] btn_s1_arb_share_counter_next_value;
  wire    [  1: 0] btn_s1_arb_share_set_values;
  wire             btn_s1_beginbursttransfer_internal;
  wire             btn_s1_begins_xfer;
  wire             btn_s1_chipselect;
  wire             btn_s1_end_xfer;
  wire             btn_s1_firsttransfer;
  wire             btn_s1_grant_vector;
  wire             btn_s1_in_a_read_cycle;
  wire             btn_s1_in_a_write_cycle;
  wire             btn_s1_irq_from_sa;
  wire             btn_s1_master_qreq_vector;
  wire             btn_s1_non_bursting_master_requests;
  wire    [ 31: 0] btn_s1_readdata_from_sa;
  reg              btn_s1_reg_firsttransfer;
  wire             btn_s1_reset_n;
  reg              btn_s1_slavearbiterlockenable;
  wire             btn_s1_slavearbiterlockenable2;
  wire             btn_s1_unreg_firsttransfer;
  wire             btn_s1_waits_for_read;
  wire             btn_s1_waits_for_write;
  wire             btn_s1_write_n;
  wire    [ 31: 0] btn_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_btn_s1;
  wire             cpu_data_master_qualified_request_btn_s1;
  wire             cpu_data_master_read_data_valid_btn_s1;
  wire             cpu_data_master_requests_btn_s1;
  wire             cpu_data_master_saved_grant_btn_s1;
  reg              d1_btn_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_btn_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_btn_s1_from_cpu_data_master;
  wire             wait_for_btn_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~btn_s1_end_xfer;
    end


  assign btn_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_btn_s1));
  //assign btn_s1_readdata_from_sa = btn_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign btn_s1_readdata_from_sa = btn_s1_readdata;

  assign cpu_data_master_requests_btn_s1 = ({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1109080) & (cpu_data_master_read | cpu_data_master_write);
  //btn_s1_arb_share_counter set values, which is an e_mux
  assign btn_s1_arb_share_set_values = 1;

  //btn_s1_non_bursting_master_requests mux, which is an e_mux
  assign btn_s1_non_bursting_master_requests = cpu_data_master_requests_btn_s1;

  //btn_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign btn_s1_any_bursting_master_saved_grant = 0;

  //btn_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign btn_s1_arb_share_counter_next_value = btn_s1_firsttransfer ? (btn_s1_arb_share_set_values - 1) : |btn_s1_arb_share_counter ? (btn_s1_arb_share_counter - 1) : 0;

  //btn_s1_allgrants all slave grants, which is an e_mux
  assign btn_s1_allgrants = |btn_s1_grant_vector;

  //btn_s1_end_xfer assignment, which is an e_assign
  assign btn_s1_end_xfer = ~(btn_s1_waits_for_read | btn_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_btn_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_btn_s1 = btn_s1_end_xfer & (~btn_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //btn_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign btn_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_btn_s1 & btn_s1_allgrants) | (end_xfer_arb_share_counter_term_btn_s1 & ~btn_s1_non_bursting_master_requests);

  //btn_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          btn_s1_arb_share_counter <= 0;
      else if (btn_s1_arb_counter_enable)
          btn_s1_arb_share_counter <= btn_s1_arb_share_counter_next_value;
    end


  //btn_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          btn_s1_slavearbiterlockenable <= 0;
      else if ((|btn_s1_master_qreq_vector & end_xfer_arb_share_counter_term_btn_s1) | (end_xfer_arb_share_counter_term_btn_s1 & ~btn_s1_non_bursting_master_requests))
          btn_s1_slavearbiterlockenable <= |btn_s1_arb_share_counter_next_value;
    end


  //cpu/data_master btn/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = btn_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //btn_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign btn_s1_slavearbiterlockenable2 = |btn_s1_arb_share_counter_next_value;

  //cpu/data_master btn/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = btn_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //btn_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign btn_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_btn_s1 = cpu_data_master_requests_btn_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_btn_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_btn_s1 = cpu_data_master_granted_btn_s1 & cpu_data_master_read & ~btn_s1_waits_for_read;

  //btn_s1_writedata mux, which is an e_mux
  assign btn_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_btn_s1 = cpu_data_master_qualified_request_btn_s1;

  //cpu/data_master saved-grant btn/s1, which is an e_assign
  assign cpu_data_master_saved_grant_btn_s1 = cpu_data_master_requests_btn_s1;

  //allow new arb cycle for btn/s1, which is an e_assign
  assign btn_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign btn_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign btn_s1_master_qreq_vector = 1;

  //btn_s1_reset_n assignment, which is an e_assign
  assign btn_s1_reset_n = reset_n;

  assign btn_s1_chipselect = cpu_data_master_granted_btn_s1;
  //btn_s1_firsttransfer first transaction, which is an e_assign
  assign btn_s1_firsttransfer = btn_s1_begins_xfer ? btn_s1_unreg_firsttransfer : btn_s1_reg_firsttransfer;

  //btn_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign btn_s1_unreg_firsttransfer = ~(btn_s1_slavearbiterlockenable & btn_s1_any_continuerequest);

  //btn_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          btn_s1_reg_firsttransfer <= 1'b1;
      else if (btn_s1_begins_xfer)
          btn_s1_reg_firsttransfer <= btn_s1_unreg_firsttransfer;
    end


  //btn_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign btn_s1_beginbursttransfer_internal = btn_s1_begins_xfer;

  //~btn_s1_write_n assignment, which is an e_mux
  assign btn_s1_write_n = ~(cpu_data_master_granted_btn_s1 & cpu_data_master_write);

  assign shifted_address_to_btn_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //btn_s1_address mux, which is an e_mux
  assign btn_s1_address = shifted_address_to_btn_s1_from_cpu_data_master >> 2;

  //d1_btn_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_btn_s1_end_xfer <= 1;
      else 
        d1_btn_s1_end_xfer <= btn_s1_end_xfer;
    end


  //btn_s1_waits_for_read in a cycle, which is an e_mux
  assign btn_s1_waits_for_read = btn_s1_in_a_read_cycle & btn_s1_begins_xfer;

  //btn_s1_in_a_read_cycle assignment, which is an e_assign
  assign btn_s1_in_a_read_cycle = cpu_data_master_granted_btn_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = btn_s1_in_a_read_cycle;

  //btn_s1_waits_for_write in a cycle, which is an e_mux
  assign btn_s1_waits_for_write = btn_s1_in_a_write_cycle & 0;

  //btn_s1_in_a_write_cycle assignment, which is an e_assign
  assign btn_s1_in_a_write_cycle = cpu_data_master_granted_btn_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = btn_s1_in_a_write_cycle;

  assign wait_for_btn_s1_counter = 0;
  //assign btn_s1_irq_from_sa = btn_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign btn_s1_irq_from_sa = btn_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //btn/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_jtag_debug_module_arbitrator (
                                          // inputs:
                                           clk,
                                           cpu_data_master_address_to_slave,
                                           cpu_data_master_byteenable,
                                           cpu_data_master_debugaccess,
                                           cpu_data_master_latency_counter,
                                           cpu_data_master_read,
                                           cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                           cpu_data_master_write,
                                           cpu_data_master_writedata,
                                           cpu_instruction_master_address_to_slave,
                                           cpu_instruction_master_latency_counter,
                                           cpu_instruction_master_read,
                                           cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                           cpu_jtag_debug_module_readdata,
                                           cpu_jtag_debug_module_resetrequest,
                                           reset_n,

                                          // outputs:
                                           cpu_data_master_granted_cpu_jtag_debug_module,
                                           cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_data_master_requests_cpu_jtag_debug_module,
                                           cpu_instruction_master_granted_cpu_jtag_debug_module,
                                           cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_instruction_master_requests_cpu_jtag_debug_module,
                                           cpu_jtag_debug_module_address,
                                           cpu_jtag_debug_module_begintransfer,
                                           cpu_jtag_debug_module_byteenable,
                                           cpu_jtag_debug_module_chipselect,
                                           cpu_jtag_debug_module_debugaccess,
                                           cpu_jtag_debug_module_readdata_from_sa,
                                           cpu_jtag_debug_module_reset_n,
                                           cpu_jtag_debug_module_resetrequest_from_sa,
                                           cpu_jtag_debug_module_write,
                                           cpu_jtag_debug_module_writedata,
                                           d1_cpu_jtag_debug_module_end_xfer
                                        )
;

  output           cpu_data_master_granted_cpu_jtag_debug_module;
  output           cpu_data_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_data_master_requests_cpu_jtag_debug_module;
  output           cpu_instruction_master_granted_cpu_jtag_debug_module;
  output           cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_instruction_master_requests_cpu_jtag_debug_module;
  output  [  8: 0] cpu_jtag_debug_module_address;
  output           cpu_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_jtag_debug_module_byteenable;
  output           cpu_jtag_debug_module_chipselect;
  output           cpu_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  output           cpu_jtag_debug_module_reset_n;
  output           cpu_jtag_debug_module_resetrequest_from_sa;
  output           cpu_jtag_debug_module_write;
  output  [ 31: 0] cpu_jtag_debug_module_writedata;
  output           d1_cpu_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_debugaccess;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 24: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  input   [ 31: 0] cpu_jtag_debug_module_readdata;
  input            cpu_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_saved_grant_cpu_jtag_debug_module;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_saved_grant_cpu_jtag_debug_module;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_allgrants;
  wire             cpu_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_jtag_debug_module_arb_addend;
  wire             cpu_jtag_debug_module_arb_counter_enable;
  reg     [  1: 0] cpu_jtag_debug_module_arb_share_counter;
  wire    [  1: 0] cpu_jtag_debug_module_arb_share_counter_next_value;
  wire    [  1: 0] cpu_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_jtag_debug_module_arb_winner;
  wire             cpu_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_jtag_debug_module_begins_xfer;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_jtag_debug_module_debugaccess;
  wire             cpu_jtag_debug_module_end_xfer;
  wire             cpu_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_jtag_debug_module_grant_vector;
  wire             cpu_jtag_debug_module_in_a_read_cycle;
  wire             cpu_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_jtag_debug_module_master_qreq_vector;
  wire             cpu_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  reg              cpu_jtag_debug_module_reg_firsttransfer;
  wire             cpu_jtag_debug_module_reset_n;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_jtag_debug_module_unreg_firsttransfer;
  wire             cpu_jtag_debug_module_waits_for_read;
  wire             cpu_jtag_debug_module_waits_for_write;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  reg              d1_cpu_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_cpu_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
  reg              last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
  wire    [ 24: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master;
  wire    [ 24: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master;
  wire             wait_for_cpu_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~cpu_jtag_debug_module_end_xfer;
    end


  assign cpu_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cpu_jtag_debug_module | cpu_instruction_master_qualified_request_cpu_jtag_debug_module));
  //assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata;

  assign cpu_data_master_requests_cpu_jtag_debug_module = ({cpu_data_master_address_to_slave[24 : 11] , 11'b0} == 25'h1108800) & (cpu_data_master_read | cpu_data_master_write);
  //cpu_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_jtag_debug_module_arb_share_set_values = 1;

  //cpu_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_jtag_debug_module_non_bursting_master_requests = cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module |
    cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_jtag_debug_module_arb_share_counter_next_value = cpu_jtag_debug_module_firsttransfer ? (cpu_jtag_debug_module_arb_share_set_values - 1) : |cpu_jtag_debug_module_arb_share_counter ? (cpu_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_jtag_debug_module_allgrants = (|cpu_jtag_debug_module_grant_vector) |
    (|cpu_jtag_debug_module_grant_vector) |
    (|cpu_jtag_debug_module_grant_vector) |
    (|cpu_jtag_debug_module_grant_vector);

  //cpu_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_jtag_debug_module_end_xfer = ~(cpu_jtag_debug_module_waits_for_read | cpu_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_jtag_debug_module = cpu_jtag_debug_module_end_xfer & (~cpu_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & cpu_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests);

  //cpu_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_jtag_debug_module_arb_counter_enable)
          cpu_jtag_debug_module_arb_share_counter <= cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests))
          cpu_jtag_debug_module_slavearbiterlockenable <= |cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu/data_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_data_master_continuerequest;

  //cpu_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_jtag_debug_module_slavearbiterlockenable2 = |cpu_jtag_debug_module_arb_share_counter_next_value;

  //cpu/data_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= cpu_instruction_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module & cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_jtag_debug_module_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_cpu_jtag_debug_module = cpu_data_master_requests_cpu_jtag_debug_module & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))) | cpu_instruction_master_arbiterlock);
  //local readdatavalid cpu_data_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux
  assign cpu_data_master_read_data_valid_cpu_jtag_debug_module = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read & ~cpu_jtag_debug_module_waits_for_read;

  //cpu_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_jtag_debug_module_writedata = cpu_data_master_writedata;

  assign cpu_instruction_master_requests_cpu_jtag_debug_module = (({cpu_instruction_master_address_to_slave[24 : 11] , 11'b0} == 25'h1108800) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= cpu_data_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_data_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module & cpu_data_master_requests_cpu_jtag_debug_module;

  assign cpu_instruction_master_qualified_request_cpu_jtag_debug_module = cpu_instruction_master_requests_cpu_jtag_debug_module & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0) | (|cpu_instruction_master_read_data_valid_sdram_s1_shift_register))) | cpu_data_master_arbiterlock);
  //local readdatavalid cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux
  assign cpu_instruction_master_read_data_valid_cpu_jtag_debug_module = cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read & ~cpu_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cpu_jtag_debug_module;

  //cpu/instruction_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[0];

  //cpu/instruction_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[0] && cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu/data_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[1] = cpu_data_master_qualified_request_cpu_jtag_debug_module;

  //cpu/data_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[1];

  //cpu/data_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[1] && cpu_data_master_requests_cpu_jtag_debug_module;

  //cpu/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_double_vector = {cpu_jtag_debug_module_master_qreq_vector, cpu_jtag_debug_module_master_qreq_vector} & ({~cpu_jtag_debug_module_master_qreq_vector, ~cpu_jtag_debug_module_master_qreq_vector} + cpu_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_jtag_debug_module_arb_winner = (cpu_jtag_debug_module_allow_new_arb_cycle & | cpu_jtag_debug_module_grant_vector) ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_jtag_debug_module_allow_new_arb_cycle)
          cpu_jtag_debug_module_saved_chosen_master_vector <= |cpu_jtag_debug_module_grant_vector ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_jtag_debug_module_grant_vector = {(cpu_jtag_debug_module_chosen_master_double_vector[1] | cpu_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_jtag_debug_module_chosen_master_double_vector[0] | cpu_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_rot_left = (cpu_jtag_debug_module_arb_winner << 1) ? (cpu_jtag_debug_module_arb_winner << 1) : 1;

  //cpu/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_jtag_debug_module_grant_vector)
          cpu_jtag_debug_module_arb_addend <= cpu_jtag_debug_module_end_xfer? cpu_jtag_debug_module_chosen_master_rot_left : cpu_jtag_debug_module_grant_vector;
    end


  assign cpu_jtag_debug_module_begintransfer = cpu_jtag_debug_module_begins_xfer;
  //cpu_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu_jtag_debug_module_reset_n = reset_n;

  //assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest;

  assign cpu_jtag_debug_module_chipselect = cpu_data_master_granted_cpu_jtag_debug_module | cpu_instruction_master_granted_cpu_jtag_debug_module;
  //cpu_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_firsttransfer = cpu_jtag_debug_module_begins_xfer ? cpu_jtag_debug_module_unreg_firsttransfer : cpu_jtag_debug_module_reg_firsttransfer;

  //cpu_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_unreg_firsttransfer = ~(cpu_jtag_debug_module_slavearbiterlockenable & cpu_jtag_debug_module_any_continuerequest);

  //cpu_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_reg_firsttransfer <= 1'b1;
      else if (cpu_jtag_debug_module_begins_xfer)
          cpu_jtag_debug_module_reg_firsttransfer <= cpu_jtag_debug_module_unreg_firsttransfer;
    end


  //cpu_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_jtag_debug_module_beginbursttransfer_internal = cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_jtag_debug_module_arbitration_holdoff_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer;

  //cpu_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_jtag_debug_module_write = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master = cpu_data_master_address_to_slave;
  //cpu_jtag_debug_module_address mux, which is an e_mux
  assign cpu_jtag_debug_module_address = (cpu_data_master_granted_cpu_jtag_debug_module)? (shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master >> 2) :
    (shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master >> 2);

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
  //d1_cpu_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_jtag_debug_module_end_xfer <= 1;
      else 
        d1_cpu_jtag_debug_module_end_xfer <= cpu_jtag_debug_module_end_xfer;
    end


  //cpu_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_read = cpu_jtag_debug_module_in_a_read_cycle & cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_read_cycle = (cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read) | (cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_jtag_debug_module_in_a_read_cycle;

  //cpu_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_write = cpu_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_write_cycle = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_jtag_debug_module_counter = 0;
  //cpu_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_jtag_debug_module_byteenable = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_byteenable :
    -1;

  //debugaccess mux, which is an e_mux
  assign cpu_jtag_debug_module_debugaccess = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu/jtag_debug_module enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_cpu_jtag_debug_module + cpu_instruction_master_granted_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_cpu_jtag_debug_module + cpu_instruction_master_saved_grant_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_data_master_arbitrator (
                                    // inputs:
                                     btn_s1_irq_from_sa,
                                     btn_s1_readdata_from_sa,
                                     clk,
                                     cpu_data_master_address,
                                     cpu_data_master_byteenable,
                                     cpu_data_master_byteenable_sdram_s1,
                                     cpu_data_master_byteenable_sram_cpu_ctrl,
                                     cpu_data_master_granted_btn_s1,
                                     cpu_data_master_granted_cpu_jtag_debug_module,
                                     cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_granted_ledg_s1,
                                     cpu_data_master_granted_ledr_s1,
                                     cpu_data_master_granted_nios_sd_card_clock_0_in,
                                     cpu_data_master_granted_onchip_mem_s1,
                                     cpu_data_master_granted_sd_card_cpu_ctrl,
                                     cpu_data_master_granted_sdram_s1,
                                     cpu_data_master_granted_sram_cpu_ctrl,
                                     cpu_data_master_granted_sseg_s1,
                                     cpu_data_master_granted_switch_s1,
                                     cpu_data_master_granted_sys_timer_s1,
                                     cpu_data_master_granted_sysid_control_slave,
                                     cpu_data_master_granted_usr_timer_s1,
                                     cpu_data_master_qualified_request_btn_s1,
                                     cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                     cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_qualified_request_ledg_s1,
                                     cpu_data_master_qualified_request_ledr_s1,
                                     cpu_data_master_qualified_request_nios_sd_card_clock_0_in,
                                     cpu_data_master_qualified_request_onchip_mem_s1,
                                     cpu_data_master_qualified_request_sd_card_cpu_ctrl,
                                     cpu_data_master_qualified_request_sdram_s1,
                                     cpu_data_master_qualified_request_sram_cpu_ctrl,
                                     cpu_data_master_qualified_request_sseg_s1,
                                     cpu_data_master_qualified_request_switch_s1,
                                     cpu_data_master_qualified_request_sys_timer_s1,
                                     cpu_data_master_qualified_request_sysid_control_slave,
                                     cpu_data_master_qualified_request_usr_timer_s1,
                                     cpu_data_master_read,
                                     cpu_data_master_read_data_valid_btn_s1,
                                     cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                     cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_read_data_valid_ledg_s1,
                                     cpu_data_master_read_data_valid_ledr_s1,
                                     cpu_data_master_read_data_valid_nios_sd_card_clock_0_in,
                                     cpu_data_master_read_data_valid_onchip_mem_s1,
                                     cpu_data_master_read_data_valid_sd_card_cpu_ctrl,
                                     cpu_data_master_read_data_valid_sdram_s1,
                                     cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                     cpu_data_master_read_data_valid_sram_cpu_ctrl,
                                     cpu_data_master_read_data_valid_sseg_s1,
                                     cpu_data_master_read_data_valid_switch_s1,
                                     cpu_data_master_read_data_valid_sys_timer_s1,
                                     cpu_data_master_read_data_valid_sysid_control_slave,
                                     cpu_data_master_read_data_valid_usr_timer_s1,
                                     cpu_data_master_requests_btn_s1,
                                     cpu_data_master_requests_cpu_jtag_debug_module,
                                     cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_requests_ledg_s1,
                                     cpu_data_master_requests_ledr_s1,
                                     cpu_data_master_requests_nios_sd_card_clock_0_in,
                                     cpu_data_master_requests_onchip_mem_s1,
                                     cpu_data_master_requests_sd_card_cpu_ctrl,
                                     cpu_data_master_requests_sdram_s1,
                                     cpu_data_master_requests_sram_cpu_ctrl,
                                     cpu_data_master_requests_sseg_s1,
                                     cpu_data_master_requests_switch_s1,
                                     cpu_data_master_requests_sys_timer_s1,
                                     cpu_data_master_requests_sysid_control_slave,
                                     cpu_data_master_requests_usr_timer_s1,
                                     cpu_data_master_write,
                                     cpu_data_master_writedata,
                                     cpu_jtag_debug_module_readdata_from_sa,
                                     d1_btn_s1_end_xfer,
                                     d1_cpu_jtag_debug_module_end_xfer,
                                     d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                     d1_ledg_s1_end_xfer,
                                     d1_ledr_s1_end_xfer,
                                     d1_nios_sd_card_clock_0_in_end_xfer,
                                     d1_onchip_mem_s1_end_xfer,
                                     d1_sd_card_cpu_ctrl_end_xfer,
                                     d1_sdram_s1_end_xfer,
                                     d1_sram_cpu_ctrl_end_xfer,
                                     d1_sseg_s1_end_xfer,
                                     d1_switch_s1_end_xfer,
                                     d1_sys_timer_s1_end_xfer,
                                     d1_sysid_control_slave_end_xfer,
                                     d1_usr_timer_s1_end_xfer,
                                     jtag_uart_avalon_jtag_slave_irq_from_sa,
                                     jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                     jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                     ledg_s1_readdata_from_sa,
                                     ledr_s1_readdata_from_sa,
                                     nios_sd_card_clock_0_in_readdata_from_sa,
                                     nios_sd_card_clock_0_in_waitrequest_from_sa,
                                     onchip_mem_s1_readdata_from_sa,
                                     reset_n,
                                     sd_card_cpu_ctrl_readdata_from_sa,
                                     sdram_s1_readdata_from_sa,
                                     sdram_s1_waitrequest_from_sa,
                                     sram_cpu_ctrl_readdata_from_sa,
                                     sseg_s1_readdata_from_sa,
                                     switch_s1_readdata_from_sa,
                                     sys_timer_s1_irq_from_sa,
                                     sys_timer_s1_readdata_from_sa,
                                     sysid_control_slave_readdata_from_sa,
                                     usr_timer_s1_irq_from_sa,
                                     usr_timer_s1_readdata_from_sa,

                                    // outputs:
                                     cpu_data_master_address_to_slave,
                                     cpu_data_master_dbs_address,
                                     cpu_data_master_dbs_write_16,
                                     cpu_data_master_irq,
                                     cpu_data_master_latency_counter,
                                     cpu_data_master_readdata,
                                     cpu_data_master_readdatavalid,
                                     cpu_data_master_waitrequest
                                  )
;

  output  [ 24: 0] cpu_data_master_address_to_slave;
  output  [  1: 0] cpu_data_master_dbs_address;
  output  [ 15: 0] cpu_data_master_dbs_write_16;
  output  [ 31: 0] cpu_data_master_irq;
  output  [  1: 0] cpu_data_master_latency_counter;
  output  [ 31: 0] cpu_data_master_readdata;
  output           cpu_data_master_readdatavalid;
  output           cpu_data_master_waitrequest;
  input            btn_s1_irq_from_sa;
  input   [ 31: 0] btn_s1_readdata_from_sa;
  input            clk;
  input   [ 24: 0] cpu_data_master_address;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_byteenable_sdram_s1;
  input   [  1: 0] cpu_data_master_byteenable_sram_cpu_ctrl;
  input            cpu_data_master_granted_btn_s1;
  input            cpu_data_master_granted_cpu_jtag_debug_module;
  input            cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_granted_ledg_s1;
  input            cpu_data_master_granted_ledr_s1;
  input            cpu_data_master_granted_nios_sd_card_clock_0_in;
  input            cpu_data_master_granted_onchip_mem_s1;
  input            cpu_data_master_granted_sd_card_cpu_ctrl;
  input            cpu_data_master_granted_sdram_s1;
  input            cpu_data_master_granted_sram_cpu_ctrl;
  input            cpu_data_master_granted_sseg_s1;
  input            cpu_data_master_granted_switch_s1;
  input            cpu_data_master_granted_sys_timer_s1;
  input            cpu_data_master_granted_sysid_control_slave;
  input            cpu_data_master_granted_usr_timer_s1;
  input            cpu_data_master_qualified_request_btn_s1;
  input            cpu_data_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_qualified_request_ledg_s1;
  input            cpu_data_master_qualified_request_ledr_s1;
  input            cpu_data_master_qualified_request_nios_sd_card_clock_0_in;
  input            cpu_data_master_qualified_request_onchip_mem_s1;
  input            cpu_data_master_qualified_request_sd_card_cpu_ctrl;
  input            cpu_data_master_qualified_request_sdram_s1;
  input            cpu_data_master_qualified_request_sram_cpu_ctrl;
  input            cpu_data_master_qualified_request_sseg_s1;
  input            cpu_data_master_qualified_request_switch_s1;
  input            cpu_data_master_qualified_request_sys_timer_s1;
  input            cpu_data_master_qualified_request_sysid_control_slave;
  input            cpu_data_master_qualified_request_usr_timer_s1;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_btn_s1;
  input            cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_read_data_valid_ledg_s1;
  input            cpu_data_master_read_data_valid_ledr_s1;
  input            cpu_data_master_read_data_valid_nios_sd_card_clock_0_in;
  input            cpu_data_master_read_data_valid_onchip_mem_s1;
  input            cpu_data_master_read_data_valid_sd_card_cpu_ctrl;
  input            cpu_data_master_read_data_valid_sdram_s1;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_read_data_valid_sram_cpu_ctrl;
  input            cpu_data_master_read_data_valid_sseg_s1;
  input            cpu_data_master_read_data_valid_switch_s1;
  input            cpu_data_master_read_data_valid_sys_timer_s1;
  input            cpu_data_master_read_data_valid_sysid_control_slave;
  input            cpu_data_master_read_data_valid_usr_timer_s1;
  input            cpu_data_master_requests_btn_s1;
  input            cpu_data_master_requests_cpu_jtag_debug_module;
  input            cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_requests_ledg_s1;
  input            cpu_data_master_requests_ledr_s1;
  input            cpu_data_master_requests_nios_sd_card_clock_0_in;
  input            cpu_data_master_requests_onchip_mem_s1;
  input            cpu_data_master_requests_sd_card_cpu_ctrl;
  input            cpu_data_master_requests_sdram_s1;
  input            cpu_data_master_requests_sram_cpu_ctrl;
  input            cpu_data_master_requests_sseg_s1;
  input            cpu_data_master_requests_switch_s1;
  input            cpu_data_master_requests_sys_timer_s1;
  input            cpu_data_master_requests_sysid_control_slave;
  input            cpu_data_master_requests_usr_timer_s1;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_btn_s1_end_xfer;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_jtag_uart_avalon_jtag_slave_end_xfer;
  input            d1_ledg_s1_end_xfer;
  input            d1_ledr_s1_end_xfer;
  input            d1_nios_sd_card_clock_0_in_end_xfer;
  input            d1_onchip_mem_s1_end_xfer;
  input            d1_sd_card_cpu_ctrl_end_xfer;
  input            d1_sdram_s1_end_xfer;
  input            d1_sram_cpu_ctrl_end_xfer;
  input            d1_sseg_s1_end_xfer;
  input            d1_switch_s1_end_xfer;
  input            d1_sys_timer_s1_end_xfer;
  input            d1_sysid_control_slave_end_xfer;
  input            d1_usr_timer_s1_end_xfer;
  input            jtag_uart_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  input   [ 31: 0] ledg_s1_readdata_from_sa;
  input   [ 31: 0] ledr_s1_readdata_from_sa;
  input   [ 31: 0] nios_sd_card_clock_0_in_readdata_from_sa;
  input            nios_sd_card_clock_0_in_waitrequest_from_sa;
  input   [ 31: 0] onchip_mem_s1_readdata_from_sa;
  input            reset_n;
  input   [ 31: 0] sd_card_cpu_ctrl_readdata_from_sa;
  input   [ 15: 0] sdram_s1_readdata_from_sa;
  input            sdram_s1_waitrequest_from_sa;
  input   [ 15: 0] sram_cpu_ctrl_readdata_from_sa;
  input   [ 31: 0] sseg_s1_readdata_from_sa;
  input   [ 31: 0] switch_s1_readdata_from_sa;
  input            sys_timer_s1_irq_from_sa;
  input   [ 15: 0] sys_timer_s1_readdata_from_sa;
  input   [ 31: 0] sysid_control_slave_readdata_from_sa;
  input            usr_timer_s1_irq_from_sa;
  input   [ 15: 0] usr_timer_s1_readdata_from_sa;

  reg              active_and_waiting_last_time;
  reg     [ 24: 0] cpu_data_master_address_last_time;
  wire    [ 24: 0] cpu_data_master_address_to_slave;
  reg     [  3: 0] cpu_data_master_byteenable_last_time;
  reg     [  1: 0] cpu_data_master_dbs_address;
  wire    [  1: 0] cpu_data_master_dbs_increment;
  reg     [  1: 0] cpu_data_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_data_master_dbs_rdv_counter_inc;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_data_master_irq;
  wire             cpu_data_master_is_granted_some_slave;
  reg     [  1: 0] cpu_data_master_latency_counter;
  wire    [  1: 0] cpu_data_master_next_dbs_rdv_counter;
  reg              cpu_data_master_read_but_no_slave_selected;
  reg              cpu_data_master_read_last_time;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_readdatavalid;
  wire             cpu_data_master_run;
  wire             cpu_data_master_waitrequest;
  reg              cpu_data_master_write_last_time;
  reg     [ 31: 0] cpu_data_master_writedata_last_time;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire    [  1: 0] latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire    [  1: 0] p1_cpu_data_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_data_master_readdatavalid;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  wire             r_3;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_data_master_qualified_request_btn_s1 | ~cpu_data_master_requests_btn_s1) & ((~cpu_data_master_qualified_request_btn_s1 | ~cpu_data_master_read | (1 & ~d1_btn_s1_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_btn_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_requests_cpu_jtag_debug_module) & (cpu_data_master_granted_cpu_jtag_debug_module | ~cpu_data_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_ledg_s1 | ~cpu_data_master_requests_ledg_s1) & ((~cpu_data_master_qualified_request_ledg_s1 | ~cpu_data_master_read | (1 & ~d1_ledg_s1_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_ledg_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_ledr_s1 | ~cpu_data_master_requests_ledr_s1) & ((~cpu_data_master_qualified_request_ledr_s1 | ~cpu_data_master_read | (1 & ~d1_ledr_s1_end_xfer & cpu_data_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_data_master_run = r_0 & r_1 & r_2 & r_3;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = ((~cpu_data_master_qualified_request_ledr_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_nios_sd_card_clock_0_in | ~cpu_data_master_requests_nios_sd_card_clock_0_in) & ((~cpu_data_master_qualified_request_nios_sd_card_clock_0_in | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~nios_sd_card_clock_0_in_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_nios_sd_card_clock_0_in | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~nios_sd_card_clock_0_in_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_onchip_mem_s1 | ~cpu_data_master_requests_onchip_mem_s1) & (cpu_data_master_granted_onchip_mem_s1 | ~cpu_data_master_qualified_request_onchip_mem_s1) & ((~cpu_data_master_qualified_request_onchip_mem_s1 | ~(cpu_data_master_read | cpu_data_master_write) | (1 & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_onchip_mem_s1 | ~(cpu_data_master_read | cpu_data_master_write) | (1 & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_sd_card_cpu_ctrl | ~cpu_data_master_requests_sd_card_cpu_ctrl) & ((~cpu_data_master_qualified_request_sd_card_cpu_ctrl | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~d1_sd_card_cpu_ctrl_end_xfer & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_sd_card_cpu_ctrl | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~d1_sd_card_cpu_ctrl_end_xfer & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_sdram_s1 | (cpu_data_master_write & !cpu_data_master_byteenable_sdram_s1 & cpu_data_master_dbs_address[1]) | ~cpu_data_master_requests_sdram_s1) & (cpu_data_master_granted_sdram_s1 | ~cpu_data_master_qualified_request_sdram_s1) & ((~cpu_data_master_qualified_request_sdram_s1 | ~cpu_data_master_read | (1 & ~sdram_s1_waitrequest_from_sa & (cpu_data_master_dbs_address[1]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sdram_s1 | ~cpu_data_master_write | (1 & ~sdram_s1_waitrequest_from_sa & (cpu_data_master_dbs_address[1]) & cpu_data_master_write))) & 1;

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = (cpu_data_master_qualified_request_sram_cpu_ctrl | (cpu_data_master_write & !cpu_data_master_byteenable_sram_cpu_ctrl & cpu_data_master_dbs_address[1]) | ~cpu_data_master_requests_sram_cpu_ctrl) & (cpu_data_master_granted_sram_cpu_ctrl | ~cpu_data_master_qualified_request_sram_cpu_ctrl) & ((~cpu_data_master_qualified_request_sram_cpu_ctrl | ~cpu_data_master_read | (1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sram_cpu_ctrl | ~cpu_data_master_write | (1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_sseg_s1 | ~cpu_data_master_requests_sseg_s1) & ((~cpu_data_master_qualified_request_sseg_s1 | ~cpu_data_master_read | (1 & ~d1_sseg_s1_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sseg_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_switch_s1 | ~cpu_data_master_requests_switch_s1) & ((~cpu_data_master_qualified_request_switch_s1 | ~cpu_data_master_read | (1 & ~d1_switch_s1_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_switch_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_sys_timer_s1 | ~cpu_data_master_requests_sys_timer_s1) & ((~cpu_data_master_qualified_request_sys_timer_s1 | ~cpu_data_master_read | (1 & ~d1_sys_timer_s1_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sys_timer_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_requests_sysid_control_slave) & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_read | (1 & ~d1_sysid_control_slave_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_write | (1 & cpu_data_master_write)));

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = 1 & (cpu_data_master_qualified_request_usr_timer_s1 | ~cpu_data_master_requests_usr_timer_s1) & ((~cpu_data_master_qualified_request_usr_timer_s1 | ~cpu_data_master_read | (1 & ~d1_usr_timer_s1_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_usr_timer_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_data_master_address_to_slave = cpu_data_master_address[24 : 0];

  //cpu_data_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_but_no_slave_selected <= 0;
      else 
        cpu_data_master_read_but_no_slave_selected <= cpu_data_master_read & cpu_data_master_run & ~cpu_data_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_data_master_is_granted_some_slave = cpu_data_master_granted_btn_s1 |
    cpu_data_master_granted_cpu_jtag_debug_module |
    cpu_data_master_granted_jtag_uart_avalon_jtag_slave |
    cpu_data_master_granted_ledg_s1 |
    cpu_data_master_granted_ledr_s1 |
    cpu_data_master_granted_nios_sd_card_clock_0_in |
    cpu_data_master_granted_onchip_mem_s1 |
    cpu_data_master_granted_sd_card_cpu_ctrl |
    cpu_data_master_granted_sdram_s1 |
    cpu_data_master_granted_sram_cpu_ctrl |
    cpu_data_master_granted_sseg_s1 |
    cpu_data_master_granted_switch_s1 |
    cpu_data_master_granted_sys_timer_s1 |
    cpu_data_master_granted_sysid_control_slave |
    cpu_data_master_granted_usr_timer_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_data_master_readdatavalid = cpu_data_master_read_data_valid_onchip_mem_s1 |
    (cpu_data_master_read_data_valid_sdram_s1 & dbs_rdv_counter_overflow) |
    (cpu_data_master_read_data_valid_sram_cpu_ctrl & dbs_rdv_counter_overflow);

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_data_master_readdatavalid = cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_btn_s1 |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_cpu_jtag_debug_module |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_ledg_s1 |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_ledr_s1 |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_nios_sd_card_clock_0_in |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_sd_card_cpu_ctrl |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_sseg_s1 |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_switch_s1 |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_sys_timer_s1 |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_sysid_control_slave |
    cpu_data_master_read_but_no_slave_selected |
    pre_flush_cpu_data_master_readdatavalid |
    cpu_data_master_read_data_valid_usr_timer_s1;

  //cpu/data_master readdata mux, which is an e_mux
  assign cpu_data_master_readdata = ({32 {~(cpu_data_master_qualified_request_btn_s1 & cpu_data_master_read)}} | btn_s1_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_cpu_jtag_debug_module & cpu_data_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave & cpu_data_master_read)}} | jtag_uart_avalon_jtag_slave_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_ledg_s1 & cpu_data_master_read)}} | ledg_s1_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_ledr_s1 & cpu_data_master_read)}} | ledr_s1_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_nios_sd_card_clock_0_in & cpu_data_master_read)}} | nios_sd_card_clock_0_in_readdata_from_sa) &
    ({32 {~cpu_data_master_read_data_valid_onchip_mem_s1}} | onchip_mem_s1_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_sd_card_cpu_ctrl & cpu_data_master_read)}} | sd_card_cpu_ctrl_readdata_from_sa) &
    ({32 {~cpu_data_master_read_data_valid_sdram_s1}} | {sdram_s1_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_data_master_read_data_valid_sram_cpu_ctrl}} | {sram_cpu_ctrl_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~(cpu_data_master_qualified_request_sseg_s1 & cpu_data_master_read)}} | sseg_s1_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_switch_s1 & cpu_data_master_read)}} | switch_s1_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_sys_timer_s1 & cpu_data_master_read)}} | sys_timer_s1_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_sysid_control_slave & cpu_data_master_read)}} | sysid_control_slave_readdata_from_sa) &
    ({32 {~(cpu_data_master_qualified_request_usr_timer_s1 & cpu_data_master_read)}} | usr_timer_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_assign
  assign cpu_data_master_waitrequest = ~cpu_data_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_latency_counter <= 0;
      else 
        cpu_data_master_latency_counter <= p1_cpu_data_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_data_master_latency_counter = ((cpu_data_master_run & cpu_data_master_read))? latency_load_value :
    (cpu_data_master_latency_counter)? cpu_data_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = ({2 {cpu_data_master_requests_onchip_mem_s1}} & 1) |
    ({2 {cpu_data_master_requests_sram_cpu_ctrl}} & 2);

  //irq assign, which is an e_assign
  assign cpu_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    btn_s1_irq_from_sa,
    jtag_uart_avalon_jtag_slave_irq_from_sa,
    usr_timer_s1_irq_from_sa,
    sys_timer_s1_irq_from_sa,
    1'b0};

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (((~0) & cpu_data_master_requests_sdram_s1 & cpu_data_master_write & !cpu_data_master_byteenable_sdram_s1)) |
    (cpu_data_master_granted_sdram_s1 & cpu_data_master_read & 1 & 1 & ~sdram_s1_waitrequest_from_sa) |
    (cpu_data_master_granted_sdram_s1 & cpu_data_master_write & 1 & 1 & ~sdram_s1_waitrequest_from_sa) |
    (((~0) & cpu_data_master_requests_sram_cpu_ctrl & cpu_data_master_write & !cpu_data_master_byteenable_sram_cpu_ctrl)) |
    (cpu_data_master_granted_sram_cpu_ctrl & cpu_data_master_read & 1 & 1) |
    (cpu_data_master_granted_sram_cpu_ctrl & cpu_data_master_write & 1 & 1);

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = (cpu_data_master_read_data_valid_sdram_s1)? sdram_s1_readdata_from_sa :
    sram_cpu_ctrl_readdata_from_sa;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_data_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //mux write dbs 1, which is an e_mux
  assign cpu_data_master_dbs_write_16 = (cpu_data_master_dbs_address[1])? cpu_data_master_writedata[31 : 16] :
    (~(cpu_data_master_dbs_address[1]))? cpu_data_master_writedata[15 : 0] :
    (cpu_data_master_dbs_address[1])? cpu_data_master_writedata[31 : 16] :
    cpu_data_master_writedata[15 : 0];

  //dbs count increment, which is an e_mux
  assign cpu_data_master_dbs_increment = (cpu_data_master_requests_sdram_s1)? 2 :
    (cpu_data_master_requests_sram_cpu_ctrl)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_data_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_data_master_dbs_address + cpu_data_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_data_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_data_master_next_dbs_rdv_counter = cpu_data_master_dbs_rdv_counter + cpu_data_master_dbs_rdv_counter_inc;

  //cpu_data_master_rdv_inc_mux, which is an e_mux
  assign cpu_data_master_dbs_rdv_counter_inc = (cpu_data_master_read_data_valid_sdram_s1)? 2 :
    2;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_data_master_read_data_valid_sdram_s1 |
    cpu_data_master_read_data_valid_sram_cpu_ctrl;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_data_master_dbs_rdv_counter <= cpu_data_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_data_master_dbs_rdv_counter[1] & ~cpu_data_master_next_dbs_rdv_counter[1];


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_data_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_address_last_time <= 0;
      else 
        cpu_data_master_address_last_time <= cpu_data_master_address;
    end


  //cpu/data_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= cpu_data_master_waitrequest & (cpu_data_master_read | cpu_data_master_write);
    end


  //cpu_data_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_data_master_address != cpu_data_master_address_last_time))
        begin
          $write("%0d ns: cpu_data_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_data_master_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_byteenable_last_time <= 0;
      else 
        cpu_data_master_byteenable_last_time <= cpu_data_master_byteenable;
    end


  //cpu_data_master_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_data_master_byteenable != cpu_data_master_byteenable_last_time))
        begin
          $write("%0d ns: cpu_data_master_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_data_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_last_time <= 0;
      else 
        cpu_data_master_read_last_time <= cpu_data_master_read;
    end


  //cpu_data_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_data_master_read != cpu_data_master_read_last_time))
        begin
          $write("%0d ns: cpu_data_master_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_data_master_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_write_last_time <= 0;
      else 
        cpu_data_master_write_last_time <= cpu_data_master_write;
    end


  //cpu_data_master_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_data_master_write != cpu_data_master_write_last_time))
        begin
          $write("%0d ns: cpu_data_master_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_data_master_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_writedata_last_time <= 0;
      else 
        cpu_data_master_writedata_last_time <= cpu_data_master_writedata;
    end


  //cpu_data_master_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_data_master_writedata != cpu_data_master_writedata_last_time) & cpu_data_master_write)
        begin
          $write("%0d ns: cpu_data_master_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_instruction_master_arbitrator (
                                           // inputs:
                                            clk,
                                            cpu_instruction_master_address,
                                            cpu_instruction_master_granted_cpu_jtag_debug_module,
                                            cpu_instruction_master_granted_onchip_mem_s1,
                                            cpu_instruction_master_granted_sdram_s1,
                                            cpu_instruction_master_granted_sram_cpu_ctrl,
                                            cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                            cpu_instruction_master_qualified_request_onchip_mem_s1,
                                            cpu_instruction_master_qualified_request_sdram_s1,
                                            cpu_instruction_master_qualified_request_sram_cpu_ctrl,
                                            cpu_instruction_master_read,
                                            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                            cpu_instruction_master_read_data_valid_onchip_mem_s1,
                                            cpu_instruction_master_read_data_valid_sdram_s1,
                                            cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                            cpu_instruction_master_read_data_valid_sram_cpu_ctrl,
                                            cpu_instruction_master_requests_cpu_jtag_debug_module,
                                            cpu_instruction_master_requests_onchip_mem_s1,
                                            cpu_instruction_master_requests_sdram_s1,
                                            cpu_instruction_master_requests_sram_cpu_ctrl,
                                            cpu_jtag_debug_module_readdata_from_sa,
                                            d1_cpu_jtag_debug_module_end_xfer,
                                            d1_onchip_mem_s1_end_xfer,
                                            d1_sdram_s1_end_xfer,
                                            d1_sram_cpu_ctrl_end_xfer,
                                            onchip_mem_s1_readdata_from_sa,
                                            reset_n,
                                            sdram_s1_readdata_from_sa,
                                            sdram_s1_waitrequest_from_sa,
                                            sram_cpu_ctrl_readdata_from_sa,

                                           // outputs:
                                            cpu_instruction_master_address_to_slave,
                                            cpu_instruction_master_dbs_address,
                                            cpu_instruction_master_latency_counter,
                                            cpu_instruction_master_readdata,
                                            cpu_instruction_master_readdatavalid,
                                            cpu_instruction_master_waitrequest
                                         )
;

  output  [ 24: 0] cpu_instruction_master_address_to_slave;
  output  [  1: 0] cpu_instruction_master_dbs_address;
  output  [  1: 0] cpu_instruction_master_latency_counter;
  output  [ 31: 0] cpu_instruction_master_readdata;
  output           cpu_instruction_master_readdatavalid;
  output           cpu_instruction_master_waitrequest;
  input            clk;
  input   [ 24: 0] cpu_instruction_master_address;
  input            cpu_instruction_master_granted_cpu_jtag_debug_module;
  input            cpu_instruction_master_granted_onchip_mem_s1;
  input            cpu_instruction_master_granted_sdram_s1;
  input            cpu_instruction_master_granted_sram_cpu_ctrl;
  input            cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_instruction_master_qualified_request_onchip_mem_s1;
  input            cpu_instruction_master_qualified_request_sdram_s1;
  input            cpu_instruction_master_qualified_request_sram_cpu_ctrl;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_instruction_master_read_data_valid_onchip_mem_s1;
  input            cpu_instruction_master_read_data_valid_sdram_s1;
  input            cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_instruction_master_read_data_valid_sram_cpu_ctrl;
  input            cpu_instruction_master_requests_cpu_jtag_debug_module;
  input            cpu_instruction_master_requests_onchip_mem_s1;
  input            cpu_instruction_master_requests_sdram_s1;
  input            cpu_instruction_master_requests_sram_cpu_ctrl;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_onchip_mem_s1_end_xfer;
  input            d1_sdram_s1_end_xfer;
  input            d1_sram_cpu_ctrl_end_xfer;
  input   [ 31: 0] onchip_mem_s1_readdata_from_sa;
  input            reset_n;
  input   [ 15: 0] sdram_s1_readdata_from_sa;
  input            sdram_s1_waitrequest_from_sa;
  input   [ 15: 0] sram_cpu_ctrl_readdata_from_sa;

  reg              active_and_waiting_last_time;
  reg     [ 24: 0] cpu_instruction_master_address_last_time;
  wire    [ 24: 0] cpu_instruction_master_address_to_slave;
  reg     [  1: 0] cpu_instruction_master_dbs_address;
  wire    [  1: 0] cpu_instruction_master_dbs_increment;
  reg     [  1: 0] cpu_instruction_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_instruction_master_dbs_rdv_counter_inc;
  wire             cpu_instruction_master_is_granted_some_slave;
  reg     [  1: 0] cpu_instruction_master_latency_counter;
  wire    [  1: 0] cpu_instruction_master_next_dbs_rdv_counter;
  reg              cpu_instruction_master_read_but_no_slave_selected;
  reg              cpu_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_run;
  wire             cpu_instruction_master_waitrequest;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire    [  1: 0] latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire    [  1: 0] p1_cpu_instruction_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_instruction_master_readdatavalid;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_requests_cpu_jtag_debug_module) & (cpu_instruction_master_granted_cpu_jtag_debug_module | ~cpu_instruction_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_instruction_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_instruction_master_run = r_0 & r_1 & r_2;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = 1 & (cpu_instruction_master_qualified_request_onchip_mem_s1 | ~cpu_instruction_master_requests_onchip_mem_s1) & (cpu_instruction_master_granted_onchip_mem_s1 | ~cpu_instruction_master_qualified_request_onchip_mem_s1) & ((~cpu_instruction_master_qualified_request_onchip_mem_s1 | ~(cpu_instruction_master_read) | (1 & (cpu_instruction_master_read)))) & 1 & (cpu_instruction_master_qualified_request_sdram_s1 | ~cpu_instruction_master_requests_sdram_s1) & (cpu_instruction_master_granted_sdram_s1 | ~cpu_instruction_master_qualified_request_sdram_s1) & ((~cpu_instruction_master_qualified_request_sdram_s1 | ~cpu_instruction_master_read | (1 & ~sdram_s1_waitrequest_from_sa & (cpu_instruction_master_dbs_address[1]) & cpu_instruction_master_read)));

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & (cpu_instruction_master_qualified_request_sram_cpu_ctrl | ~cpu_instruction_master_requests_sram_cpu_ctrl) & (cpu_instruction_master_granted_sram_cpu_ctrl | ~cpu_instruction_master_qualified_request_sram_cpu_ctrl) & ((~cpu_instruction_master_qualified_request_sram_cpu_ctrl | ~cpu_instruction_master_read | (1 & (cpu_instruction_master_dbs_address[1]) & cpu_instruction_master_read)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_instruction_master_address_to_slave = cpu_instruction_master_address[24 : 0];

  //cpu_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_but_no_slave_selected <= 0;
      else 
        cpu_instruction_master_read_but_no_slave_selected <= cpu_instruction_master_read & cpu_instruction_master_run & ~cpu_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_instruction_master_is_granted_some_slave = cpu_instruction_master_granted_cpu_jtag_debug_module |
    cpu_instruction_master_granted_onchip_mem_s1 |
    cpu_instruction_master_granted_sdram_s1 |
    cpu_instruction_master_granted_sram_cpu_ctrl;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_instruction_master_readdatavalid = cpu_instruction_master_read_data_valid_onchip_mem_s1 |
    (cpu_instruction_master_read_data_valid_sdram_s1 & dbs_rdv_counter_overflow) |
    (cpu_instruction_master_read_data_valid_sram_cpu_ctrl & dbs_rdv_counter_overflow);

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_instruction_master_readdatavalid = cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_data_valid_cpu_jtag_debug_module |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid;

  //cpu/instruction_master readdata mux, which is an e_mux
  assign cpu_instruction_master_readdata = ({32 {~(cpu_instruction_master_qualified_request_cpu_jtag_debug_module & cpu_instruction_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_instruction_master_read_data_valid_onchip_mem_s1}} | onchip_mem_s1_readdata_from_sa) &
    ({32 {~cpu_instruction_master_read_data_valid_sdram_s1}} | {sdram_s1_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_instruction_master_read_data_valid_sram_cpu_ctrl}} | {sram_cpu_ctrl_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0});

  //actual waitrequest port, which is an e_assign
  assign cpu_instruction_master_waitrequest = ~cpu_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_latency_counter <= 0;
      else 
        cpu_instruction_master_latency_counter <= p1_cpu_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_instruction_master_latency_counter = ((cpu_instruction_master_run & cpu_instruction_master_read))? latency_load_value :
    (cpu_instruction_master_latency_counter)? cpu_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = ({2 {cpu_instruction_master_requests_onchip_mem_s1}} & 1) |
    ({2 {cpu_instruction_master_requests_sram_cpu_ctrl}} & 2);

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = (cpu_instruction_master_read_data_valid_sdram_s1)? sdram_s1_readdata_from_sa :
    sram_cpu_ctrl_readdata_from_sa;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //dbs count increment, which is an e_mux
  assign cpu_instruction_master_dbs_increment = (cpu_instruction_master_requests_sdram_s1)? 2 :
    (cpu_instruction_master_requests_sram_cpu_ctrl)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_instruction_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_instruction_master_dbs_address + cpu_instruction_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_instruction_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_instruction_master_next_dbs_rdv_counter = cpu_instruction_master_dbs_rdv_counter + cpu_instruction_master_dbs_rdv_counter_inc;

  //cpu_instruction_master_rdv_inc_mux, which is an e_mux
  assign cpu_instruction_master_dbs_rdv_counter_inc = (cpu_instruction_master_read_data_valid_sdram_s1)? 2 :
    2;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_instruction_master_read_data_valid_sdram_s1 |
    cpu_instruction_master_read_data_valid_sram_cpu_ctrl;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_instruction_master_dbs_rdv_counter <= cpu_instruction_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_instruction_master_dbs_rdv_counter[1] & ~cpu_instruction_master_next_dbs_rdv_counter[1];

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (cpu_instruction_master_granted_sdram_s1 & cpu_instruction_master_read & 1 & 1 & ~sdram_s1_waitrequest_from_sa) |
    (cpu_instruction_master_granted_sram_cpu_ctrl & cpu_instruction_master_read & 1 & 1);


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_address_last_time <= 0;
      else 
        cpu_instruction_master_address_last_time <= cpu_instruction_master_address;
    end


  //cpu/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= cpu_instruction_master_waitrequest & (cpu_instruction_master_read);
    end


  //cpu_instruction_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_address != cpu_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_last_time <= 0;
      else 
        cpu_instruction_master_read_last_time <= cpu_instruction_master_read;
    end


  //cpu_instruction_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_read != cpu_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module jtag_uart_avalon_jtag_slave_arbitrator (
                                                // inputs:
                                                 clk,
                                                 cpu_data_master_address_to_slave,
                                                 cpu_data_master_latency_counter,
                                                 cpu_data_master_read,
                                                 cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                                 cpu_data_master_write,
                                                 cpu_data_master_writedata,
                                                 jtag_uart_avalon_jtag_slave_dataavailable,
                                                 jtag_uart_avalon_jtag_slave_irq,
                                                 jtag_uart_avalon_jtag_slave_readdata,
                                                 jtag_uart_avalon_jtag_slave_readyfordata,
                                                 jtag_uart_avalon_jtag_slave_waitrequest,
                                                 reset_n,

                                                // outputs:
                                                 cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                                 d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                                 jtag_uart_avalon_jtag_slave_address,
                                                 jtag_uart_avalon_jtag_slave_chipselect,
                                                 jtag_uart_avalon_jtag_slave_dataavailable_from_sa,
                                                 jtag_uart_avalon_jtag_slave_irq_from_sa,
                                                 jtag_uart_avalon_jtag_slave_read_n,
                                                 jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_readyfordata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_reset_n,
                                                 jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                                 jtag_uart_avalon_jtag_slave_write_n,
                                                 jtag_uart_avalon_jtag_slave_writedata
                                              )
;

  output           cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  output           d1_jtag_uart_avalon_jtag_slave_end_xfer;
  output           jtag_uart_avalon_jtag_slave_address;
  output           jtag_uart_avalon_jtag_slave_chipselect;
  output           jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  output           jtag_uart_avalon_jtag_slave_irq_from_sa;
  output           jtag_uart_avalon_jtag_slave_read_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  output           jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  output           jtag_uart_avalon_jtag_slave_reset_n;
  output           jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  output           jtag_uart_avalon_jtag_slave_write_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            jtag_uart_avalon_jtag_slave_dataavailable;
  input            jtag_uart_avalon_jtag_slave_irq;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  input            jtag_uart_avalon_jtag_slave_readyfordata;
  input            jtag_uart_avalon_jtag_slave_waitrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave;
  reg              d1_jtag_uart_avalon_jtag_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_allgrants;
  wire             jtag_uart_avalon_jtag_slave_allow_new_arb_cycle;
  wire             jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant;
  wire             jtag_uart_avalon_jtag_slave_any_continuerequest;
  wire             jtag_uart_avalon_jtag_slave_arb_counter_enable;
  reg     [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_counter;
  wire    [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
  wire    [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_set_values;
  wire             jtag_uart_avalon_jtag_slave_beginbursttransfer_internal;
  wire             jtag_uart_avalon_jtag_slave_begins_xfer;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_end_xfer;
  wire             jtag_uart_avalon_jtag_slave_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_grant_vector;
  wire             jtag_uart_avalon_jtag_slave_in_a_read_cycle;
  wire             jtag_uart_avalon_jtag_slave_in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_master_qreq_vector;
  wire             jtag_uart_avalon_jtag_slave_non_bursting_master_requests;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  reg              jtag_uart_avalon_jtag_slave_reg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  reg              jtag_uart_avalon_jtag_slave_slavearbiterlockenable;
  wire             jtag_uart_avalon_jtag_slave_slavearbiterlockenable2;
  wire             jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_waits_for_read;
  wire             jtag_uart_avalon_jtag_slave_waits_for_write;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [ 24: 0] shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master;
  wire             wait_for_jtag_uart_avalon_jtag_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~jtag_uart_avalon_jtag_slave_end_xfer;
    end


  assign jtag_uart_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave));
  //assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata;

  assign cpu_data_master_requests_jtag_uart_avalon_jtag_slave = ({cpu_data_master_address_to_slave[24 : 3] , 3'b0} == 25'h11090b0) & (cpu_data_master_read | cpu_data_master_write);
  //assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable;

  //assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata;

  //assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest;

  //jtag_uart_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_arb_share_set_values = 1;

  //jtag_uart_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_non_bursting_master_requests = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant = 0;

  //jtag_uart_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_avalon_jtag_slave_firsttransfer ? (jtag_uart_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_avalon_jtag_slave_arb_share_counter ? (jtag_uart_avalon_jtag_slave_arb_share_counter - 1) : 0;

  //jtag_uart_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_allgrants = |jtag_uart_avalon_jtag_slave_grant_vector;

  //jtag_uart_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_end_xfer = ~(jtag_uart_avalon_jtag_slave_waits_for_read | jtag_uart_avalon_jtag_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave = jtag_uart_avalon_jtag_slave_end_xfer & (~jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //jtag_uart_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & jtag_uart_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests);

  //jtag_uart_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= 0;
      else if (jtag_uart_avalon_jtag_slave_arb_counter_enable)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= 0;
      else if ((|jtag_uart_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests))
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = jtag_uart_avalon_jtag_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;

  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave, which is an e_mux
  assign cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read & ~jtag_uart_avalon_jtag_slave_waits_for_read;

  //jtag_uart_avalon_jtag_slave_writedata mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_jtag_uart_avalon_jtag_slave = cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;

  //cpu/data_master saved-grant jtag_uart/avalon_jtag_slave, which is an e_assign
  assign cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //allow new arb cycle for jtag_uart/avalon_jtag_slave, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign jtag_uart_avalon_jtag_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign jtag_uart_avalon_jtag_slave_master_qreq_vector = 1;

  //jtag_uart_avalon_jtag_slave_reset_n assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_reset_n = reset_n;

  assign jtag_uart_avalon_jtag_slave_chipselect = cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  //jtag_uart_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_firsttransfer = jtag_uart_avalon_jtag_slave_begins_xfer ? jtag_uart_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_avalon_jtag_slave_reg_firsttransfer;

  //jtag_uart_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_avalon_jtag_slave_any_continuerequest);

  //jtag_uart_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
      else if (jtag_uart_avalon_jtag_slave_begins_xfer)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
    end


  //jtag_uart_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_avalon_jtag_slave_begins_xfer;

  //~jtag_uart_avalon_jtag_slave_read_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_read_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read);

  //~jtag_uart_avalon_jtag_slave_write_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_write_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write);

  assign shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //jtag_uart_avalon_jtag_slave_address mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_address = shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master >> 2;

  //d1_jtag_uart_avalon_jtag_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_jtag_uart_avalon_jtag_slave_end_xfer <= 1;
      else 
        d1_jtag_uart_avalon_jtag_slave_end_xfer <= jtag_uart_avalon_jtag_slave_end_xfer;
    end


  //jtag_uart_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_read = jtag_uart_avalon_jtag_slave_in_a_read_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_read_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = jtag_uart_avalon_jtag_slave_in_a_read_cycle;

  //jtag_uart_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_write = jtag_uart_avalon_jtag_slave_in_a_write_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_write_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = jtag_uart_avalon_jtag_slave_in_a_write_cycle;

  assign wait_for_jtag_uart_avalon_jtag_slave_counter = 0;
  //assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart/avalon_jtag_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module ledg_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_latency_counter,
                             cpu_data_master_read,
                             cpu_data_master_read_data_valid_sdram_s1_shift_register,
                             cpu_data_master_write,
                             cpu_data_master_writedata,
                             ledg_s1_readdata,
                             reset_n,

                            // outputs:
                             cpu_data_master_granted_ledg_s1,
                             cpu_data_master_qualified_request_ledg_s1,
                             cpu_data_master_read_data_valid_ledg_s1,
                             cpu_data_master_requests_ledg_s1,
                             d1_ledg_s1_end_xfer,
                             ledg_s1_address,
                             ledg_s1_chipselect,
                             ledg_s1_readdata_from_sa,
                             ledg_s1_reset_n,
                             ledg_s1_write_n,
                             ledg_s1_writedata
                          )
;

  output           cpu_data_master_granted_ledg_s1;
  output           cpu_data_master_qualified_request_ledg_s1;
  output           cpu_data_master_read_data_valid_ledg_s1;
  output           cpu_data_master_requests_ledg_s1;
  output           d1_ledg_s1_end_xfer;
  output  [  1: 0] ledg_s1_address;
  output           ledg_s1_chipselect;
  output  [ 31: 0] ledg_s1_readdata_from_sa;
  output           ledg_s1_reset_n;
  output           ledg_s1_write_n;
  output  [ 31: 0] ledg_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] ledg_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_ledg_s1;
  wire             cpu_data_master_qualified_request_ledg_s1;
  wire             cpu_data_master_read_data_valid_ledg_s1;
  wire             cpu_data_master_requests_ledg_s1;
  wire             cpu_data_master_saved_grant_ledg_s1;
  reg              d1_ledg_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_ledg_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] ledg_s1_address;
  wire             ledg_s1_allgrants;
  wire             ledg_s1_allow_new_arb_cycle;
  wire             ledg_s1_any_bursting_master_saved_grant;
  wire             ledg_s1_any_continuerequest;
  wire             ledg_s1_arb_counter_enable;
  reg     [  1: 0] ledg_s1_arb_share_counter;
  wire    [  1: 0] ledg_s1_arb_share_counter_next_value;
  wire    [  1: 0] ledg_s1_arb_share_set_values;
  wire             ledg_s1_beginbursttransfer_internal;
  wire             ledg_s1_begins_xfer;
  wire             ledg_s1_chipselect;
  wire             ledg_s1_end_xfer;
  wire             ledg_s1_firsttransfer;
  wire             ledg_s1_grant_vector;
  wire             ledg_s1_in_a_read_cycle;
  wire             ledg_s1_in_a_write_cycle;
  wire             ledg_s1_master_qreq_vector;
  wire             ledg_s1_non_bursting_master_requests;
  wire    [ 31: 0] ledg_s1_readdata_from_sa;
  reg              ledg_s1_reg_firsttransfer;
  wire             ledg_s1_reset_n;
  reg              ledg_s1_slavearbiterlockenable;
  wire             ledg_s1_slavearbiterlockenable2;
  wire             ledg_s1_unreg_firsttransfer;
  wire             ledg_s1_waits_for_read;
  wire             ledg_s1_waits_for_write;
  wire             ledg_s1_write_n;
  wire    [ 31: 0] ledg_s1_writedata;
  wire    [ 24: 0] shifted_address_to_ledg_s1_from_cpu_data_master;
  wire             wait_for_ledg_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~ledg_s1_end_xfer;
    end


  assign ledg_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_ledg_s1));
  //assign ledg_s1_readdata_from_sa = ledg_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign ledg_s1_readdata_from_sa = ledg_s1_readdata;

  assign cpu_data_master_requests_ledg_s1 = ({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1109040) & (cpu_data_master_read | cpu_data_master_write);
  //ledg_s1_arb_share_counter set values, which is an e_mux
  assign ledg_s1_arb_share_set_values = 1;

  //ledg_s1_non_bursting_master_requests mux, which is an e_mux
  assign ledg_s1_non_bursting_master_requests = cpu_data_master_requests_ledg_s1;

  //ledg_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign ledg_s1_any_bursting_master_saved_grant = 0;

  //ledg_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign ledg_s1_arb_share_counter_next_value = ledg_s1_firsttransfer ? (ledg_s1_arb_share_set_values - 1) : |ledg_s1_arb_share_counter ? (ledg_s1_arb_share_counter - 1) : 0;

  //ledg_s1_allgrants all slave grants, which is an e_mux
  assign ledg_s1_allgrants = |ledg_s1_grant_vector;

  //ledg_s1_end_xfer assignment, which is an e_assign
  assign ledg_s1_end_xfer = ~(ledg_s1_waits_for_read | ledg_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_ledg_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_ledg_s1 = ledg_s1_end_xfer & (~ledg_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //ledg_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign ledg_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_ledg_s1 & ledg_s1_allgrants) | (end_xfer_arb_share_counter_term_ledg_s1 & ~ledg_s1_non_bursting_master_requests);

  //ledg_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ledg_s1_arb_share_counter <= 0;
      else if (ledg_s1_arb_counter_enable)
          ledg_s1_arb_share_counter <= ledg_s1_arb_share_counter_next_value;
    end


  //ledg_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ledg_s1_slavearbiterlockenable <= 0;
      else if ((|ledg_s1_master_qreq_vector & end_xfer_arb_share_counter_term_ledg_s1) | (end_xfer_arb_share_counter_term_ledg_s1 & ~ledg_s1_non_bursting_master_requests))
          ledg_s1_slavearbiterlockenable <= |ledg_s1_arb_share_counter_next_value;
    end


  //cpu/data_master ledg/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = ledg_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //ledg_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign ledg_s1_slavearbiterlockenable2 = |ledg_s1_arb_share_counter_next_value;

  //cpu/data_master ledg/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = ledg_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //ledg_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign ledg_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_ledg_s1 = cpu_data_master_requests_ledg_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_ledg_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_ledg_s1 = cpu_data_master_granted_ledg_s1 & cpu_data_master_read & ~ledg_s1_waits_for_read;

  //ledg_s1_writedata mux, which is an e_mux
  assign ledg_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_ledg_s1 = cpu_data_master_qualified_request_ledg_s1;

  //cpu/data_master saved-grant ledg/s1, which is an e_assign
  assign cpu_data_master_saved_grant_ledg_s1 = cpu_data_master_requests_ledg_s1;

  //allow new arb cycle for ledg/s1, which is an e_assign
  assign ledg_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign ledg_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign ledg_s1_master_qreq_vector = 1;

  //ledg_s1_reset_n assignment, which is an e_assign
  assign ledg_s1_reset_n = reset_n;

  assign ledg_s1_chipselect = cpu_data_master_granted_ledg_s1;
  //ledg_s1_firsttransfer first transaction, which is an e_assign
  assign ledg_s1_firsttransfer = ledg_s1_begins_xfer ? ledg_s1_unreg_firsttransfer : ledg_s1_reg_firsttransfer;

  //ledg_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign ledg_s1_unreg_firsttransfer = ~(ledg_s1_slavearbiterlockenable & ledg_s1_any_continuerequest);

  //ledg_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ledg_s1_reg_firsttransfer <= 1'b1;
      else if (ledg_s1_begins_xfer)
          ledg_s1_reg_firsttransfer <= ledg_s1_unreg_firsttransfer;
    end


  //ledg_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign ledg_s1_beginbursttransfer_internal = ledg_s1_begins_xfer;

  //~ledg_s1_write_n assignment, which is an e_mux
  assign ledg_s1_write_n = ~(cpu_data_master_granted_ledg_s1 & cpu_data_master_write);

  assign shifted_address_to_ledg_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //ledg_s1_address mux, which is an e_mux
  assign ledg_s1_address = shifted_address_to_ledg_s1_from_cpu_data_master >> 2;

  //d1_ledg_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_ledg_s1_end_xfer <= 1;
      else 
        d1_ledg_s1_end_xfer <= ledg_s1_end_xfer;
    end


  //ledg_s1_waits_for_read in a cycle, which is an e_mux
  assign ledg_s1_waits_for_read = ledg_s1_in_a_read_cycle & ledg_s1_begins_xfer;

  //ledg_s1_in_a_read_cycle assignment, which is an e_assign
  assign ledg_s1_in_a_read_cycle = cpu_data_master_granted_ledg_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = ledg_s1_in_a_read_cycle;

  //ledg_s1_waits_for_write in a cycle, which is an e_mux
  assign ledg_s1_waits_for_write = ledg_s1_in_a_write_cycle & 0;

  //ledg_s1_in_a_write_cycle assignment, which is an e_assign
  assign ledg_s1_in_a_write_cycle = cpu_data_master_granted_ledg_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = ledg_s1_in_a_write_cycle;

  assign wait_for_ledg_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //ledg/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module ledr_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_latency_counter,
                             cpu_data_master_read,
                             cpu_data_master_read_data_valid_sdram_s1_shift_register,
                             cpu_data_master_write,
                             cpu_data_master_writedata,
                             ledr_s1_readdata,
                             reset_n,

                            // outputs:
                             cpu_data_master_granted_ledr_s1,
                             cpu_data_master_qualified_request_ledr_s1,
                             cpu_data_master_read_data_valid_ledr_s1,
                             cpu_data_master_requests_ledr_s1,
                             d1_ledr_s1_end_xfer,
                             ledr_s1_address,
                             ledr_s1_chipselect,
                             ledr_s1_readdata_from_sa,
                             ledr_s1_reset_n,
                             ledr_s1_write_n,
                             ledr_s1_writedata
                          )
;

  output           cpu_data_master_granted_ledr_s1;
  output           cpu_data_master_qualified_request_ledr_s1;
  output           cpu_data_master_read_data_valid_ledr_s1;
  output           cpu_data_master_requests_ledr_s1;
  output           d1_ledr_s1_end_xfer;
  output  [  1: 0] ledr_s1_address;
  output           ledr_s1_chipselect;
  output  [ 31: 0] ledr_s1_readdata_from_sa;
  output           ledr_s1_reset_n;
  output           ledr_s1_write_n;
  output  [ 31: 0] ledr_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] ledr_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_ledr_s1;
  wire             cpu_data_master_qualified_request_ledr_s1;
  wire             cpu_data_master_read_data_valid_ledr_s1;
  wire             cpu_data_master_requests_ledr_s1;
  wire             cpu_data_master_saved_grant_ledr_s1;
  reg              d1_ledr_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_ledr_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] ledr_s1_address;
  wire             ledr_s1_allgrants;
  wire             ledr_s1_allow_new_arb_cycle;
  wire             ledr_s1_any_bursting_master_saved_grant;
  wire             ledr_s1_any_continuerequest;
  wire             ledr_s1_arb_counter_enable;
  reg     [  1: 0] ledr_s1_arb_share_counter;
  wire    [  1: 0] ledr_s1_arb_share_counter_next_value;
  wire    [  1: 0] ledr_s1_arb_share_set_values;
  wire             ledr_s1_beginbursttransfer_internal;
  wire             ledr_s1_begins_xfer;
  wire             ledr_s1_chipselect;
  wire             ledr_s1_end_xfer;
  wire             ledr_s1_firsttransfer;
  wire             ledr_s1_grant_vector;
  wire             ledr_s1_in_a_read_cycle;
  wire             ledr_s1_in_a_write_cycle;
  wire             ledr_s1_master_qreq_vector;
  wire             ledr_s1_non_bursting_master_requests;
  wire    [ 31: 0] ledr_s1_readdata_from_sa;
  reg              ledr_s1_reg_firsttransfer;
  wire             ledr_s1_reset_n;
  reg              ledr_s1_slavearbiterlockenable;
  wire             ledr_s1_slavearbiterlockenable2;
  wire             ledr_s1_unreg_firsttransfer;
  wire             ledr_s1_waits_for_read;
  wire             ledr_s1_waits_for_write;
  wire             ledr_s1_write_n;
  wire    [ 31: 0] ledr_s1_writedata;
  wire    [ 24: 0] shifted_address_to_ledr_s1_from_cpu_data_master;
  wire             wait_for_ledr_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~ledr_s1_end_xfer;
    end


  assign ledr_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_ledr_s1));
  //assign ledr_s1_readdata_from_sa = ledr_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign ledr_s1_readdata_from_sa = ledr_s1_readdata;

  assign cpu_data_master_requests_ledr_s1 = ({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1109050) & (cpu_data_master_read | cpu_data_master_write);
  //ledr_s1_arb_share_counter set values, which is an e_mux
  assign ledr_s1_arb_share_set_values = 1;

  //ledr_s1_non_bursting_master_requests mux, which is an e_mux
  assign ledr_s1_non_bursting_master_requests = cpu_data_master_requests_ledr_s1;

  //ledr_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign ledr_s1_any_bursting_master_saved_grant = 0;

  //ledr_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign ledr_s1_arb_share_counter_next_value = ledr_s1_firsttransfer ? (ledr_s1_arb_share_set_values - 1) : |ledr_s1_arb_share_counter ? (ledr_s1_arb_share_counter - 1) : 0;

  //ledr_s1_allgrants all slave grants, which is an e_mux
  assign ledr_s1_allgrants = |ledr_s1_grant_vector;

  //ledr_s1_end_xfer assignment, which is an e_assign
  assign ledr_s1_end_xfer = ~(ledr_s1_waits_for_read | ledr_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_ledr_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_ledr_s1 = ledr_s1_end_xfer & (~ledr_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //ledr_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign ledr_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_ledr_s1 & ledr_s1_allgrants) | (end_xfer_arb_share_counter_term_ledr_s1 & ~ledr_s1_non_bursting_master_requests);

  //ledr_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ledr_s1_arb_share_counter <= 0;
      else if (ledr_s1_arb_counter_enable)
          ledr_s1_arb_share_counter <= ledr_s1_arb_share_counter_next_value;
    end


  //ledr_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ledr_s1_slavearbiterlockenable <= 0;
      else if ((|ledr_s1_master_qreq_vector & end_xfer_arb_share_counter_term_ledr_s1) | (end_xfer_arb_share_counter_term_ledr_s1 & ~ledr_s1_non_bursting_master_requests))
          ledr_s1_slavearbiterlockenable <= |ledr_s1_arb_share_counter_next_value;
    end


  //cpu/data_master ledr/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = ledr_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //ledr_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign ledr_s1_slavearbiterlockenable2 = |ledr_s1_arb_share_counter_next_value;

  //cpu/data_master ledr/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = ledr_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //ledr_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign ledr_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_ledr_s1 = cpu_data_master_requests_ledr_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_ledr_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_ledr_s1 = cpu_data_master_granted_ledr_s1 & cpu_data_master_read & ~ledr_s1_waits_for_read;

  //ledr_s1_writedata mux, which is an e_mux
  assign ledr_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_ledr_s1 = cpu_data_master_qualified_request_ledr_s1;

  //cpu/data_master saved-grant ledr/s1, which is an e_assign
  assign cpu_data_master_saved_grant_ledr_s1 = cpu_data_master_requests_ledr_s1;

  //allow new arb cycle for ledr/s1, which is an e_assign
  assign ledr_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign ledr_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign ledr_s1_master_qreq_vector = 1;

  //ledr_s1_reset_n assignment, which is an e_assign
  assign ledr_s1_reset_n = reset_n;

  assign ledr_s1_chipselect = cpu_data_master_granted_ledr_s1;
  //ledr_s1_firsttransfer first transaction, which is an e_assign
  assign ledr_s1_firsttransfer = ledr_s1_begins_xfer ? ledr_s1_unreg_firsttransfer : ledr_s1_reg_firsttransfer;

  //ledr_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign ledr_s1_unreg_firsttransfer = ~(ledr_s1_slavearbiterlockenable & ledr_s1_any_continuerequest);

  //ledr_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ledr_s1_reg_firsttransfer <= 1'b1;
      else if (ledr_s1_begins_xfer)
          ledr_s1_reg_firsttransfer <= ledr_s1_unreg_firsttransfer;
    end


  //ledr_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign ledr_s1_beginbursttransfer_internal = ledr_s1_begins_xfer;

  //~ledr_s1_write_n assignment, which is an e_mux
  assign ledr_s1_write_n = ~(cpu_data_master_granted_ledr_s1 & cpu_data_master_write);

  assign shifted_address_to_ledr_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //ledr_s1_address mux, which is an e_mux
  assign ledr_s1_address = shifted_address_to_ledr_s1_from_cpu_data_master >> 2;

  //d1_ledr_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_ledr_s1_end_xfer <= 1;
      else 
        d1_ledr_s1_end_xfer <= ledr_s1_end_xfer;
    end


  //ledr_s1_waits_for_read in a cycle, which is an e_mux
  assign ledr_s1_waits_for_read = ledr_s1_in_a_read_cycle & ledr_s1_begins_xfer;

  //ledr_s1_in_a_read_cycle assignment, which is an e_assign
  assign ledr_s1_in_a_read_cycle = cpu_data_master_granted_ledr_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = ledr_s1_in_a_read_cycle;

  //ledr_s1_waits_for_write in a cycle, which is an e_mux
  assign ledr_s1_waits_for_write = ledr_s1_in_a_write_cycle & 0;

  //ledr_s1_in_a_write_cycle assignment, which is an e_assign
  assign ledr_s1_in_a_write_cycle = cpu_data_master_granted_ledr_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = ledr_s1_in_a_write_cycle;

  assign wait_for_ledr_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //ledr/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nios_sd_card_clock_0_in_arbitrator (
                                            // inputs:
                                             clk,
                                             cpu_data_master_address_to_slave,
                                             cpu_data_master_byteenable,
                                             cpu_data_master_latency_counter,
                                             cpu_data_master_read,
                                             cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                             cpu_data_master_write,
                                             cpu_data_master_writedata,
                                             nios_sd_card_clock_0_in_endofpacket,
                                             nios_sd_card_clock_0_in_readdata,
                                             nios_sd_card_clock_0_in_waitrequest,
                                             reset_n,

                                            // outputs:
                                             cpu_data_master_granted_nios_sd_card_clock_0_in,
                                             cpu_data_master_qualified_request_nios_sd_card_clock_0_in,
                                             cpu_data_master_read_data_valid_nios_sd_card_clock_0_in,
                                             cpu_data_master_requests_nios_sd_card_clock_0_in,
                                             d1_nios_sd_card_clock_0_in_end_xfer,
                                             nios_sd_card_clock_0_in_address,
                                             nios_sd_card_clock_0_in_byteenable,
                                             nios_sd_card_clock_0_in_endofpacket_from_sa,
                                             nios_sd_card_clock_0_in_nativeaddress,
                                             nios_sd_card_clock_0_in_read,
                                             nios_sd_card_clock_0_in_readdata_from_sa,
                                             nios_sd_card_clock_0_in_reset_n,
                                             nios_sd_card_clock_0_in_waitrequest_from_sa,
                                             nios_sd_card_clock_0_in_write,
                                             nios_sd_card_clock_0_in_writedata
                                          )
;

  output           cpu_data_master_granted_nios_sd_card_clock_0_in;
  output           cpu_data_master_qualified_request_nios_sd_card_clock_0_in;
  output           cpu_data_master_read_data_valid_nios_sd_card_clock_0_in;
  output           cpu_data_master_requests_nios_sd_card_clock_0_in;
  output           d1_nios_sd_card_clock_0_in_end_xfer;
  output  [  3: 0] nios_sd_card_clock_0_in_address;
  output  [  3: 0] nios_sd_card_clock_0_in_byteenable;
  output           nios_sd_card_clock_0_in_endofpacket_from_sa;
  output  [  1: 0] nios_sd_card_clock_0_in_nativeaddress;
  output           nios_sd_card_clock_0_in_read;
  output  [ 31: 0] nios_sd_card_clock_0_in_readdata_from_sa;
  output           nios_sd_card_clock_0_in_reset_n;
  output           nios_sd_card_clock_0_in_waitrequest_from_sa;
  output           nios_sd_card_clock_0_in_write;
  output  [ 31: 0] nios_sd_card_clock_0_in_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            nios_sd_card_clock_0_in_endofpacket;
  input   [ 31: 0] nios_sd_card_clock_0_in_readdata;
  input            nios_sd_card_clock_0_in_waitrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_nios_sd_card_clock_0_in;
  wire             cpu_data_master_qualified_request_nios_sd_card_clock_0_in;
  wire             cpu_data_master_read_data_valid_nios_sd_card_clock_0_in;
  wire             cpu_data_master_requests_nios_sd_card_clock_0_in;
  wire             cpu_data_master_saved_grant_nios_sd_card_clock_0_in;
  reg              d1_nios_sd_card_clock_0_in_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_nios_sd_card_clock_0_in;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  3: 0] nios_sd_card_clock_0_in_address;
  wire             nios_sd_card_clock_0_in_allgrants;
  wire             nios_sd_card_clock_0_in_allow_new_arb_cycle;
  wire             nios_sd_card_clock_0_in_any_bursting_master_saved_grant;
  wire             nios_sd_card_clock_0_in_any_continuerequest;
  wire             nios_sd_card_clock_0_in_arb_counter_enable;
  reg     [  1: 0] nios_sd_card_clock_0_in_arb_share_counter;
  wire    [  1: 0] nios_sd_card_clock_0_in_arb_share_counter_next_value;
  wire    [  1: 0] nios_sd_card_clock_0_in_arb_share_set_values;
  wire             nios_sd_card_clock_0_in_beginbursttransfer_internal;
  wire             nios_sd_card_clock_0_in_begins_xfer;
  wire    [  3: 0] nios_sd_card_clock_0_in_byteenable;
  wire             nios_sd_card_clock_0_in_end_xfer;
  wire             nios_sd_card_clock_0_in_endofpacket_from_sa;
  wire             nios_sd_card_clock_0_in_firsttransfer;
  wire             nios_sd_card_clock_0_in_grant_vector;
  wire             nios_sd_card_clock_0_in_in_a_read_cycle;
  wire             nios_sd_card_clock_0_in_in_a_write_cycle;
  wire             nios_sd_card_clock_0_in_master_qreq_vector;
  wire    [  1: 0] nios_sd_card_clock_0_in_nativeaddress;
  wire             nios_sd_card_clock_0_in_non_bursting_master_requests;
  wire             nios_sd_card_clock_0_in_read;
  wire    [ 31: 0] nios_sd_card_clock_0_in_readdata_from_sa;
  reg              nios_sd_card_clock_0_in_reg_firsttransfer;
  wire             nios_sd_card_clock_0_in_reset_n;
  reg              nios_sd_card_clock_0_in_slavearbiterlockenable;
  wire             nios_sd_card_clock_0_in_slavearbiterlockenable2;
  wire             nios_sd_card_clock_0_in_unreg_firsttransfer;
  wire             nios_sd_card_clock_0_in_waitrequest_from_sa;
  wire             nios_sd_card_clock_0_in_waits_for_read;
  wire             nios_sd_card_clock_0_in_waits_for_write;
  wire             nios_sd_card_clock_0_in_write;
  wire    [ 31: 0] nios_sd_card_clock_0_in_writedata;
  wire             wait_for_nios_sd_card_clock_0_in_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~nios_sd_card_clock_0_in_end_xfer;
    end


  assign nios_sd_card_clock_0_in_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_nios_sd_card_clock_0_in));
  //assign nios_sd_card_clock_0_in_readdata_from_sa = nios_sd_card_clock_0_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign nios_sd_card_clock_0_in_readdata_from_sa = nios_sd_card_clock_0_in_readdata;

  assign cpu_data_master_requests_nios_sd_card_clock_0_in = ({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1109090) & (cpu_data_master_read | cpu_data_master_write);
  //assign nios_sd_card_clock_0_in_waitrequest_from_sa = nios_sd_card_clock_0_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign nios_sd_card_clock_0_in_waitrequest_from_sa = nios_sd_card_clock_0_in_waitrequest;

  //nios_sd_card_clock_0_in_arb_share_counter set values, which is an e_mux
  assign nios_sd_card_clock_0_in_arb_share_set_values = 1;

  //nios_sd_card_clock_0_in_non_bursting_master_requests mux, which is an e_mux
  assign nios_sd_card_clock_0_in_non_bursting_master_requests = cpu_data_master_requests_nios_sd_card_clock_0_in;

  //nios_sd_card_clock_0_in_any_bursting_master_saved_grant mux, which is an e_mux
  assign nios_sd_card_clock_0_in_any_bursting_master_saved_grant = 0;

  //nios_sd_card_clock_0_in_arb_share_counter_next_value assignment, which is an e_assign
  assign nios_sd_card_clock_0_in_arb_share_counter_next_value = nios_sd_card_clock_0_in_firsttransfer ? (nios_sd_card_clock_0_in_arb_share_set_values - 1) : |nios_sd_card_clock_0_in_arb_share_counter ? (nios_sd_card_clock_0_in_arb_share_counter - 1) : 0;

  //nios_sd_card_clock_0_in_allgrants all slave grants, which is an e_mux
  assign nios_sd_card_clock_0_in_allgrants = |nios_sd_card_clock_0_in_grant_vector;

  //nios_sd_card_clock_0_in_end_xfer assignment, which is an e_assign
  assign nios_sd_card_clock_0_in_end_xfer = ~(nios_sd_card_clock_0_in_waits_for_read | nios_sd_card_clock_0_in_waits_for_write);

  //end_xfer_arb_share_counter_term_nios_sd_card_clock_0_in arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_nios_sd_card_clock_0_in = nios_sd_card_clock_0_in_end_xfer & (~nios_sd_card_clock_0_in_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //nios_sd_card_clock_0_in_arb_share_counter arbitration counter enable, which is an e_assign
  assign nios_sd_card_clock_0_in_arb_counter_enable = (end_xfer_arb_share_counter_term_nios_sd_card_clock_0_in & nios_sd_card_clock_0_in_allgrants) | (end_xfer_arb_share_counter_term_nios_sd_card_clock_0_in & ~nios_sd_card_clock_0_in_non_bursting_master_requests);

  //nios_sd_card_clock_0_in_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_in_arb_share_counter <= 0;
      else if (nios_sd_card_clock_0_in_arb_counter_enable)
          nios_sd_card_clock_0_in_arb_share_counter <= nios_sd_card_clock_0_in_arb_share_counter_next_value;
    end


  //nios_sd_card_clock_0_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_in_slavearbiterlockenable <= 0;
      else if ((|nios_sd_card_clock_0_in_master_qreq_vector & end_xfer_arb_share_counter_term_nios_sd_card_clock_0_in) | (end_xfer_arb_share_counter_term_nios_sd_card_clock_0_in & ~nios_sd_card_clock_0_in_non_bursting_master_requests))
          nios_sd_card_clock_0_in_slavearbiterlockenable <= |nios_sd_card_clock_0_in_arb_share_counter_next_value;
    end


  //cpu/data_master nios_sd_card_clock_0/in arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = nios_sd_card_clock_0_in_slavearbiterlockenable & cpu_data_master_continuerequest;

  //nios_sd_card_clock_0_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign nios_sd_card_clock_0_in_slavearbiterlockenable2 = |nios_sd_card_clock_0_in_arb_share_counter_next_value;

  //cpu/data_master nios_sd_card_clock_0/in arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = nios_sd_card_clock_0_in_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //nios_sd_card_clock_0_in_any_continuerequest at least one master continues requesting, which is an e_assign
  assign nios_sd_card_clock_0_in_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_nios_sd_card_clock_0_in = cpu_data_master_requests_nios_sd_card_clock_0_in & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_nios_sd_card_clock_0_in, which is an e_mux
  assign cpu_data_master_read_data_valid_nios_sd_card_clock_0_in = cpu_data_master_granted_nios_sd_card_clock_0_in & cpu_data_master_read & ~nios_sd_card_clock_0_in_waits_for_read;

  //nios_sd_card_clock_0_in_writedata mux, which is an e_mux
  assign nios_sd_card_clock_0_in_writedata = cpu_data_master_writedata;

  //assign nios_sd_card_clock_0_in_endofpacket_from_sa = nios_sd_card_clock_0_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign nios_sd_card_clock_0_in_endofpacket_from_sa = nios_sd_card_clock_0_in_endofpacket;

  //master is always granted when requested
  assign cpu_data_master_granted_nios_sd_card_clock_0_in = cpu_data_master_qualified_request_nios_sd_card_clock_0_in;

  //cpu/data_master saved-grant nios_sd_card_clock_0/in, which is an e_assign
  assign cpu_data_master_saved_grant_nios_sd_card_clock_0_in = cpu_data_master_requests_nios_sd_card_clock_0_in;

  //allow new arb cycle for nios_sd_card_clock_0/in, which is an e_assign
  assign nios_sd_card_clock_0_in_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign nios_sd_card_clock_0_in_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign nios_sd_card_clock_0_in_master_qreq_vector = 1;

  //nios_sd_card_clock_0_in_reset_n assignment, which is an e_assign
  assign nios_sd_card_clock_0_in_reset_n = reset_n;

  //nios_sd_card_clock_0_in_firsttransfer first transaction, which is an e_assign
  assign nios_sd_card_clock_0_in_firsttransfer = nios_sd_card_clock_0_in_begins_xfer ? nios_sd_card_clock_0_in_unreg_firsttransfer : nios_sd_card_clock_0_in_reg_firsttransfer;

  //nios_sd_card_clock_0_in_unreg_firsttransfer first transaction, which is an e_assign
  assign nios_sd_card_clock_0_in_unreg_firsttransfer = ~(nios_sd_card_clock_0_in_slavearbiterlockenable & nios_sd_card_clock_0_in_any_continuerequest);

  //nios_sd_card_clock_0_in_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_in_reg_firsttransfer <= 1'b1;
      else if (nios_sd_card_clock_0_in_begins_xfer)
          nios_sd_card_clock_0_in_reg_firsttransfer <= nios_sd_card_clock_0_in_unreg_firsttransfer;
    end


  //nios_sd_card_clock_0_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign nios_sd_card_clock_0_in_beginbursttransfer_internal = nios_sd_card_clock_0_in_begins_xfer;

  //nios_sd_card_clock_0_in_read assignment, which is an e_mux
  assign nios_sd_card_clock_0_in_read = cpu_data_master_granted_nios_sd_card_clock_0_in & cpu_data_master_read;

  //nios_sd_card_clock_0_in_write assignment, which is an e_mux
  assign nios_sd_card_clock_0_in_write = cpu_data_master_granted_nios_sd_card_clock_0_in & cpu_data_master_write;

  //nios_sd_card_clock_0_in_address mux, which is an e_mux
  assign nios_sd_card_clock_0_in_address = cpu_data_master_address_to_slave;

  //slaveid nios_sd_card_clock_0_in_nativeaddress nativeaddress mux, which is an e_mux
  assign nios_sd_card_clock_0_in_nativeaddress = cpu_data_master_address_to_slave >> 2;

  //d1_nios_sd_card_clock_0_in_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_nios_sd_card_clock_0_in_end_xfer <= 1;
      else 
        d1_nios_sd_card_clock_0_in_end_xfer <= nios_sd_card_clock_0_in_end_xfer;
    end


  //nios_sd_card_clock_0_in_waits_for_read in a cycle, which is an e_mux
  assign nios_sd_card_clock_0_in_waits_for_read = nios_sd_card_clock_0_in_in_a_read_cycle & nios_sd_card_clock_0_in_waitrequest_from_sa;

  //nios_sd_card_clock_0_in_in_a_read_cycle assignment, which is an e_assign
  assign nios_sd_card_clock_0_in_in_a_read_cycle = cpu_data_master_granted_nios_sd_card_clock_0_in & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = nios_sd_card_clock_0_in_in_a_read_cycle;

  //nios_sd_card_clock_0_in_waits_for_write in a cycle, which is an e_mux
  assign nios_sd_card_clock_0_in_waits_for_write = nios_sd_card_clock_0_in_in_a_write_cycle & nios_sd_card_clock_0_in_waitrequest_from_sa;

  //nios_sd_card_clock_0_in_in_a_write_cycle assignment, which is an e_assign
  assign nios_sd_card_clock_0_in_in_a_write_cycle = cpu_data_master_granted_nios_sd_card_clock_0_in & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = nios_sd_card_clock_0_in_in_a_write_cycle;

  assign wait_for_nios_sd_card_clock_0_in_counter = 0;
  //nios_sd_card_clock_0_in_byteenable byte enable port mux, which is an e_mux
  assign nios_sd_card_clock_0_in_byteenable = (cpu_data_master_granted_nios_sd_card_clock_0_in)? cpu_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //nios_sd_card_clock_0/in enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nios_sd_card_clock_0_out_arbitrator (
                                             // inputs:
                                              clk,
                                              d1_pll_pll_slave_end_xfer,
                                              nios_sd_card_clock_0_out_address,
                                              nios_sd_card_clock_0_out_byteenable,
                                              nios_sd_card_clock_0_out_granted_pll_pll_slave,
                                              nios_sd_card_clock_0_out_qualified_request_pll_pll_slave,
                                              nios_sd_card_clock_0_out_read,
                                              nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave,
                                              nios_sd_card_clock_0_out_requests_pll_pll_slave,
                                              nios_sd_card_clock_0_out_write,
                                              nios_sd_card_clock_0_out_writedata,
                                              pll_pll_slave_readdata_from_sa,
                                              reset_n,

                                             // outputs:
                                              nios_sd_card_clock_0_out_address_to_slave,
                                              nios_sd_card_clock_0_out_readdata,
                                              nios_sd_card_clock_0_out_reset_n,
                                              nios_sd_card_clock_0_out_waitrequest
                                           )
;

  output  [  3: 0] nios_sd_card_clock_0_out_address_to_slave;
  output  [ 31: 0] nios_sd_card_clock_0_out_readdata;
  output           nios_sd_card_clock_0_out_reset_n;
  output           nios_sd_card_clock_0_out_waitrequest;
  input            clk;
  input            d1_pll_pll_slave_end_xfer;
  input   [  3: 0] nios_sd_card_clock_0_out_address;
  input   [  3: 0] nios_sd_card_clock_0_out_byteenable;
  input            nios_sd_card_clock_0_out_granted_pll_pll_slave;
  input            nios_sd_card_clock_0_out_qualified_request_pll_pll_slave;
  input            nios_sd_card_clock_0_out_read;
  input            nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave;
  input            nios_sd_card_clock_0_out_requests_pll_pll_slave;
  input            nios_sd_card_clock_0_out_write;
  input   [ 31: 0] nios_sd_card_clock_0_out_writedata;
  input   [ 31: 0] pll_pll_slave_readdata_from_sa;
  input            reset_n;

  reg              active_and_waiting_last_time;
  reg     [  3: 0] nios_sd_card_clock_0_out_address_last_time;
  wire    [  3: 0] nios_sd_card_clock_0_out_address_to_slave;
  reg     [  3: 0] nios_sd_card_clock_0_out_byteenable_last_time;
  reg              nios_sd_card_clock_0_out_read_last_time;
  wire    [ 31: 0] nios_sd_card_clock_0_out_readdata;
  wire             nios_sd_card_clock_0_out_reset_n;
  wire             nios_sd_card_clock_0_out_run;
  wire             nios_sd_card_clock_0_out_waitrequest;
  reg              nios_sd_card_clock_0_out_write_last_time;
  reg     [ 31: 0] nios_sd_card_clock_0_out_writedata_last_time;
  wire             r_1;
  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = 1 & ((~nios_sd_card_clock_0_out_qualified_request_pll_pll_slave | ~(nios_sd_card_clock_0_out_read | nios_sd_card_clock_0_out_write) | (1 & (nios_sd_card_clock_0_out_read | nios_sd_card_clock_0_out_write)))) & ((~nios_sd_card_clock_0_out_qualified_request_pll_pll_slave | ~(nios_sd_card_clock_0_out_read | nios_sd_card_clock_0_out_write) | (1 & (nios_sd_card_clock_0_out_read | nios_sd_card_clock_0_out_write))));

  //cascaded wait assignment, which is an e_assign
  assign nios_sd_card_clock_0_out_run = r_1;

  //optimize select-logic by passing only those address bits which matter.
  assign nios_sd_card_clock_0_out_address_to_slave = nios_sd_card_clock_0_out_address;

  //nios_sd_card_clock_0/out readdata mux, which is an e_mux
  assign nios_sd_card_clock_0_out_readdata = pll_pll_slave_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign nios_sd_card_clock_0_out_waitrequest = ~nios_sd_card_clock_0_out_run;

  //nios_sd_card_clock_0_out_reset_n assignment, which is an e_assign
  assign nios_sd_card_clock_0_out_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //nios_sd_card_clock_0_out_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_out_address_last_time <= 0;
      else 
        nios_sd_card_clock_0_out_address_last_time <= nios_sd_card_clock_0_out_address;
    end


  //nios_sd_card_clock_0/out waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= nios_sd_card_clock_0_out_waitrequest & (nios_sd_card_clock_0_out_read | nios_sd_card_clock_0_out_write);
    end


  //nios_sd_card_clock_0_out_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (nios_sd_card_clock_0_out_address != nios_sd_card_clock_0_out_address_last_time))
        begin
          $write("%0d ns: nios_sd_card_clock_0_out_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //nios_sd_card_clock_0_out_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_out_byteenable_last_time <= 0;
      else 
        nios_sd_card_clock_0_out_byteenable_last_time <= nios_sd_card_clock_0_out_byteenable;
    end


  //nios_sd_card_clock_0_out_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (nios_sd_card_clock_0_out_byteenable != nios_sd_card_clock_0_out_byteenable_last_time))
        begin
          $write("%0d ns: nios_sd_card_clock_0_out_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //nios_sd_card_clock_0_out_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_out_read_last_time <= 0;
      else 
        nios_sd_card_clock_0_out_read_last_time <= nios_sd_card_clock_0_out_read;
    end


  //nios_sd_card_clock_0_out_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (nios_sd_card_clock_0_out_read != nios_sd_card_clock_0_out_read_last_time))
        begin
          $write("%0d ns: nios_sd_card_clock_0_out_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //nios_sd_card_clock_0_out_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_out_write_last_time <= 0;
      else 
        nios_sd_card_clock_0_out_write_last_time <= nios_sd_card_clock_0_out_write;
    end


  //nios_sd_card_clock_0_out_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (nios_sd_card_clock_0_out_write != nios_sd_card_clock_0_out_write_last_time))
        begin
          $write("%0d ns: nios_sd_card_clock_0_out_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //nios_sd_card_clock_0_out_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nios_sd_card_clock_0_out_writedata_last_time <= 0;
      else 
        nios_sd_card_clock_0_out_writedata_last_time <= nios_sd_card_clock_0_out_writedata;
    end


  //nios_sd_card_clock_0_out_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (nios_sd_card_clock_0_out_writedata != nios_sd_card_clock_0_out_writedata_last_time) & nios_sd_card_clock_0_out_write)
        begin
          $write("%0d ns: nios_sd_card_clock_0_out_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module onchip_mem_s1_arbitrator (
                                  // inputs:
                                   clk,
                                   cpu_data_master_address_to_slave,
                                   cpu_data_master_byteenable,
                                   cpu_data_master_latency_counter,
                                   cpu_data_master_read,
                                   cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                   cpu_data_master_write,
                                   cpu_data_master_writedata,
                                   cpu_instruction_master_address_to_slave,
                                   cpu_instruction_master_latency_counter,
                                   cpu_instruction_master_read,
                                   cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                   onchip_mem_s1_readdata,
                                   reset_n,

                                  // outputs:
                                   cpu_data_master_granted_onchip_mem_s1,
                                   cpu_data_master_qualified_request_onchip_mem_s1,
                                   cpu_data_master_read_data_valid_onchip_mem_s1,
                                   cpu_data_master_requests_onchip_mem_s1,
                                   cpu_instruction_master_granted_onchip_mem_s1,
                                   cpu_instruction_master_qualified_request_onchip_mem_s1,
                                   cpu_instruction_master_read_data_valid_onchip_mem_s1,
                                   cpu_instruction_master_requests_onchip_mem_s1,
                                   d1_onchip_mem_s1_end_xfer,
                                   onchip_mem_s1_address,
                                   onchip_mem_s1_byteenable,
                                   onchip_mem_s1_chipselect,
                                   onchip_mem_s1_clken,
                                   onchip_mem_s1_readdata_from_sa,
                                   onchip_mem_s1_reset,
                                   onchip_mem_s1_write,
                                   onchip_mem_s1_writedata
                                )
;

  output           cpu_data_master_granted_onchip_mem_s1;
  output           cpu_data_master_qualified_request_onchip_mem_s1;
  output           cpu_data_master_read_data_valid_onchip_mem_s1;
  output           cpu_data_master_requests_onchip_mem_s1;
  output           cpu_instruction_master_granted_onchip_mem_s1;
  output           cpu_instruction_master_qualified_request_onchip_mem_s1;
  output           cpu_instruction_master_read_data_valid_onchip_mem_s1;
  output           cpu_instruction_master_requests_onchip_mem_s1;
  output           d1_onchip_mem_s1_end_xfer;
  output  [  8: 0] onchip_mem_s1_address;
  output  [  3: 0] onchip_mem_s1_byteenable;
  output           onchip_mem_s1_chipselect;
  output           onchip_mem_s1_clken;
  output  [ 31: 0] onchip_mem_s1_readdata_from_sa;
  output           onchip_mem_s1_reset;
  output           onchip_mem_s1_write;
  output  [ 31: 0] onchip_mem_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 24: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  input   [ 31: 0] onchip_mem_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_onchip_mem_s1;
  wire             cpu_data_master_qualified_request_onchip_mem_s1;
  wire             cpu_data_master_read_data_valid_onchip_mem_s1;
  reg              cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;
  wire             cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in;
  wire             cpu_data_master_requests_onchip_mem_s1;
  wire             cpu_data_master_saved_grant_onchip_mem_s1;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_onchip_mem_s1;
  wire             cpu_instruction_master_qualified_request_onchip_mem_s1;
  wire             cpu_instruction_master_read_data_valid_onchip_mem_s1;
  reg              cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;
  wire             cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in;
  wire             cpu_instruction_master_requests_onchip_mem_s1;
  wire             cpu_instruction_master_saved_grant_onchip_mem_s1;
  reg              d1_onchip_mem_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_onchip_mem_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_onchip_mem_s1;
  reg              last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1;
  wire    [  8: 0] onchip_mem_s1_address;
  wire             onchip_mem_s1_allgrants;
  wire             onchip_mem_s1_allow_new_arb_cycle;
  wire             onchip_mem_s1_any_bursting_master_saved_grant;
  wire             onchip_mem_s1_any_continuerequest;
  reg     [  1: 0] onchip_mem_s1_arb_addend;
  wire             onchip_mem_s1_arb_counter_enable;
  reg     [  1: 0] onchip_mem_s1_arb_share_counter;
  wire    [  1: 0] onchip_mem_s1_arb_share_counter_next_value;
  wire    [  1: 0] onchip_mem_s1_arb_share_set_values;
  wire    [  1: 0] onchip_mem_s1_arb_winner;
  wire             onchip_mem_s1_arbitration_holdoff_internal;
  wire             onchip_mem_s1_beginbursttransfer_internal;
  wire             onchip_mem_s1_begins_xfer;
  wire    [  3: 0] onchip_mem_s1_byteenable;
  wire             onchip_mem_s1_chipselect;
  wire    [  3: 0] onchip_mem_s1_chosen_master_double_vector;
  wire    [  1: 0] onchip_mem_s1_chosen_master_rot_left;
  wire             onchip_mem_s1_clken;
  wire             onchip_mem_s1_end_xfer;
  wire             onchip_mem_s1_firsttransfer;
  wire    [  1: 0] onchip_mem_s1_grant_vector;
  wire             onchip_mem_s1_in_a_read_cycle;
  wire             onchip_mem_s1_in_a_write_cycle;
  wire    [  1: 0] onchip_mem_s1_master_qreq_vector;
  wire             onchip_mem_s1_non_bursting_master_requests;
  wire    [ 31: 0] onchip_mem_s1_readdata_from_sa;
  reg              onchip_mem_s1_reg_firsttransfer;
  wire             onchip_mem_s1_reset;
  reg     [  1: 0] onchip_mem_s1_saved_chosen_master_vector;
  reg              onchip_mem_s1_slavearbiterlockenable;
  wire             onchip_mem_s1_slavearbiterlockenable2;
  wire             onchip_mem_s1_unreg_firsttransfer;
  wire             onchip_mem_s1_waits_for_read;
  wire             onchip_mem_s1_waits_for_write;
  wire             onchip_mem_s1_write;
  wire    [ 31: 0] onchip_mem_s1_writedata;
  wire             p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;
  wire             p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;
  wire    [ 24: 0] shifted_address_to_onchip_mem_s1_from_cpu_data_master;
  wire    [ 24: 0] shifted_address_to_onchip_mem_s1_from_cpu_instruction_master;
  wire             wait_for_onchip_mem_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~onchip_mem_s1_end_xfer;
    end


  assign onchip_mem_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_onchip_mem_s1 | cpu_instruction_master_qualified_request_onchip_mem_s1));
  //assign onchip_mem_s1_readdata_from_sa = onchip_mem_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign onchip_mem_s1_readdata_from_sa = onchip_mem_s1_readdata;

  assign cpu_data_master_requests_onchip_mem_s1 = ({cpu_data_master_address_to_slave[24 : 11] , 11'b0} == 25'h0) & (cpu_data_master_read | cpu_data_master_write);
  //onchip_mem_s1_arb_share_counter set values, which is an e_mux
  assign onchip_mem_s1_arb_share_set_values = 1;

  //onchip_mem_s1_non_bursting_master_requests mux, which is an e_mux
  assign onchip_mem_s1_non_bursting_master_requests = cpu_data_master_requests_onchip_mem_s1 |
    cpu_instruction_master_requests_onchip_mem_s1 |
    cpu_data_master_requests_onchip_mem_s1 |
    cpu_instruction_master_requests_onchip_mem_s1;

  //onchip_mem_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign onchip_mem_s1_any_bursting_master_saved_grant = 0;

  //onchip_mem_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign onchip_mem_s1_arb_share_counter_next_value = onchip_mem_s1_firsttransfer ? (onchip_mem_s1_arb_share_set_values - 1) : |onchip_mem_s1_arb_share_counter ? (onchip_mem_s1_arb_share_counter - 1) : 0;

  //onchip_mem_s1_allgrants all slave grants, which is an e_mux
  assign onchip_mem_s1_allgrants = (|onchip_mem_s1_grant_vector) |
    (|onchip_mem_s1_grant_vector) |
    (|onchip_mem_s1_grant_vector) |
    (|onchip_mem_s1_grant_vector);

  //onchip_mem_s1_end_xfer assignment, which is an e_assign
  assign onchip_mem_s1_end_xfer = ~(onchip_mem_s1_waits_for_read | onchip_mem_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_onchip_mem_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_onchip_mem_s1 = onchip_mem_s1_end_xfer & (~onchip_mem_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //onchip_mem_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign onchip_mem_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_mem_s1 & onchip_mem_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_mem_s1 & ~onchip_mem_s1_non_bursting_master_requests);

  //onchip_mem_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_arb_share_counter <= 0;
      else if (onchip_mem_s1_arb_counter_enable)
          onchip_mem_s1_arb_share_counter <= onchip_mem_s1_arb_share_counter_next_value;
    end


  //onchip_mem_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_slavearbiterlockenable <= 0;
      else if ((|onchip_mem_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_mem_s1) | (end_xfer_arb_share_counter_term_onchip_mem_s1 & ~onchip_mem_s1_non_bursting_master_requests))
          onchip_mem_s1_slavearbiterlockenable <= |onchip_mem_s1_arb_share_counter_next_value;
    end


  //cpu/data_master onchip_mem/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = onchip_mem_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //onchip_mem_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign onchip_mem_s1_slavearbiterlockenable2 = |onchip_mem_s1_arb_share_counter_next_value;

  //cpu/data_master onchip_mem/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = onchip_mem_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master onchip_mem/s1 arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = onchip_mem_s1_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master onchip_mem/s1 arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = onchip_mem_s1_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted onchip_mem/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 <= 0;
      else 
        last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 <= cpu_instruction_master_saved_grant_onchip_mem_s1 ? 1 : (onchip_mem_s1_arbitration_holdoff_internal | ~cpu_instruction_master_requests_onchip_mem_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 & cpu_instruction_master_requests_onchip_mem_s1;

  //onchip_mem_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign onchip_mem_s1_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_onchip_mem_s1 = cpu_data_master_requests_onchip_mem_s1 & ~((cpu_data_master_read & ((1 < cpu_data_master_latency_counter) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))) | cpu_instruction_master_arbiterlock);
  //cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_read & ~onchip_mem_s1_waits_for_read;

  //shift register p1 cpu_data_master_read_data_valid_onchip_mem_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register = {cpu_data_master_read_data_valid_onchip_mem_s1_shift_register, cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in};

  //cpu_data_master_read_data_valid_onchip_mem_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_data_valid_onchip_mem_s1_shift_register <= 0;
      else 
        cpu_data_master_read_data_valid_onchip_mem_s1_shift_register <= p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;
    end


  //local readdatavalid cpu_data_master_read_data_valid_onchip_mem_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_onchip_mem_s1 = cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;

  //onchip_mem_s1_writedata mux, which is an e_mux
  assign onchip_mem_s1_writedata = cpu_data_master_writedata;

  //mux onchip_mem_s1_clken, which is an e_mux
  assign onchip_mem_s1_clken = 1'b1;

  assign cpu_instruction_master_requests_onchip_mem_s1 = (({cpu_instruction_master_address_to_slave[24 : 11] , 11'b0} == 25'h0) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted onchip_mem/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 <= 0;
      else 
        last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 <= cpu_data_master_saved_grant_onchip_mem_s1 ? 1 : (onchip_mem_s1_arbitration_holdoff_internal | ~cpu_data_master_requests_onchip_mem_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_onchip_mem_s1;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 & cpu_data_master_requests_onchip_mem_s1;

  assign cpu_instruction_master_qualified_request_onchip_mem_s1 = cpu_instruction_master_requests_onchip_mem_s1 & ~((cpu_instruction_master_read & ((1 < cpu_instruction_master_latency_counter) | (|cpu_instruction_master_read_data_valid_sdram_s1_shift_register))) | cpu_data_master_arbiterlock);
  //cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in = cpu_instruction_master_granted_onchip_mem_s1 & cpu_instruction_master_read & ~onchip_mem_s1_waits_for_read;

  //shift register p1 cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register = {cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register, cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in};

  //cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register <= 0;
      else 
        cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;
    end


  //local readdatavalid cpu_instruction_master_read_data_valid_onchip_mem_s1, which is an e_mux
  assign cpu_instruction_master_read_data_valid_onchip_mem_s1 = cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;

  //allow new arb cycle for onchip_mem/s1, which is an e_assign
  assign onchip_mem_s1_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for onchip_mem/s1, which is an e_assign
  assign onchip_mem_s1_master_qreq_vector[0] = cpu_instruction_master_qualified_request_onchip_mem_s1;

  //cpu/instruction_master grant onchip_mem/s1, which is an e_assign
  assign cpu_instruction_master_granted_onchip_mem_s1 = onchip_mem_s1_grant_vector[0];

  //cpu/instruction_master saved-grant onchip_mem/s1, which is an e_assign
  assign cpu_instruction_master_saved_grant_onchip_mem_s1 = onchip_mem_s1_arb_winner[0] && cpu_instruction_master_requests_onchip_mem_s1;

  //cpu/data_master assignment into master qualified-requests vector for onchip_mem/s1, which is an e_assign
  assign onchip_mem_s1_master_qreq_vector[1] = cpu_data_master_qualified_request_onchip_mem_s1;

  //cpu/data_master grant onchip_mem/s1, which is an e_assign
  assign cpu_data_master_granted_onchip_mem_s1 = onchip_mem_s1_grant_vector[1];

  //cpu/data_master saved-grant onchip_mem/s1, which is an e_assign
  assign cpu_data_master_saved_grant_onchip_mem_s1 = onchip_mem_s1_arb_winner[1] && cpu_data_master_requests_onchip_mem_s1;

  //onchip_mem/s1 chosen-master double-vector, which is an e_assign
  assign onchip_mem_s1_chosen_master_double_vector = {onchip_mem_s1_master_qreq_vector, onchip_mem_s1_master_qreq_vector} & ({~onchip_mem_s1_master_qreq_vector, ~onchip_mem_s1_master_qreq_vector} + onchip_mem_s1_arb_addend);

  //stable onehot encoding of arb winner
  assign onchip_mem_s1_arb_winner = (onchip_mem_s1_allow_new_arb_cycle & | onchip_mem_s1_grant_vector) ? onchip_mem_s1_grant_vector : onchip_mem_s1_saved_chosen_master_vector;

  //saved onchip_mem_s1_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_saved_chosen_master_vector <= 0;
      else if (onchip_mem_s1_allow_new_arb_cycle)
          onchip_mem_s1_saved_chosen_master_vector <= |onchip_mem_s1_grant_vector ? onchip_mem_s1_grant_vector : onchip_mem_s1_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign onchip_mem_s1_grant_vector = {(onchip_mem_s1_chosen_master_double_vector[1] | onchip_mem_s1_chosen_master_double_vector[3]),
    (onchip_mem_s1_chosen_master_double_vector[0] | onchip_mem_s1_chosen_master_double_vector[2])};

  //onchip_mem/s1 chosen master rotated left, which is an e_assign
  assign onchip_mem_s1_chosen_master_rot_left = (onchip_mem_s1_arb_winner << 1) ? (onchip_mem_s1_arb_winner << 1) : 1;

  //onchip_mem/s1's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_arb_addend <= 1;
      else if (|onchip_mem_s1_grant_vector)
          onchip_mem_s1_arb_addend <= onchip_mem_s1_end_xfer? onchip_mem_s1_chosen_master_rot_left : onchip_mem_s1_grant_vector;
    end


  //~onchip_mem_s1_reset assignment, which is an e_assign
  assign onchip_mem_s1_reset = ~reset_n;

  assign onchip_mem_s1_chipselect = cpu_data_master_granted_onchip_mem_s1 | cpu_instruction_master_granted_onchip_mem_s1;
  //onchip_mem_s1_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_s1_firsttransfer = onchip_mem_s1_begins_xfer ? onchip_mem_s1_unreg_firsttransfer : onchip_mem_s1_reg_firsttransfer;

  //onchip_mem_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_s1_unreg_firsttransfer = ~(onchip_mem_s1_slavearbiterlockenable & onchip_mem_s1_any_continuerequest);

  //onchip_mem_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_reg_firsttransfer <= 1'b1;
      else if (onchip_mem_s1_begins_xfer)
          onchip_mem_s1_reg_firsttransfer <= onchip_mem_s1_unreg_firsttransfer;
    end


  //onchip_mem_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign onchip_mem_s1_beginbursttransfer_internal = onchip_mem_s1_begins_xfer;

  //onchip_mem_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign onchip_mem_s1_arbitration_holdoff_internal = onchip_mem_s1_begins_xfer & onchip_mem_s1_firsttransfer;

  //onchip_mem_s1_write assignment, which is an e_mux
  assign onchip_mem_s1_write = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_write;

  assign shifted_address_to_onchip_mem_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //onchip_mem_s1_address mux, which is an e_mux
  assign onchip_mem_s1_address = (cpu_data_master_granted_onchip_mem_s1)? (shifted_address_to_onchip_mem_s1_from_cpu_data_master >> 2) :
    (shifted_address_to_onchip_mem_s1_from_cpu_instruction_master >> 2);

  assign shifted_address_to_onchip_mem_s1_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
  //d1_onchip_mem_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_onchip_mem_s1_end_xfer <= 1;
      else 
        d1_onchip_mem_s1_end_xfer <= onchip_mem_s1_end_xfer;
    end


  //onchip_mem_s1_waits_for_read in a cycle, which is an e_mux
  assign onchip_mem_s1_waits_for_read = onchip_mem_s1_in_a_read_cycle & 0;

  //onchip_mem_s1_in_a_read_cycle assignment, which is an e_assign
  assign onchip_mem_s1_in_a_read_cycle = (cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_onchip_mem_s1 & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = onchip_mem_s1_in_a_read_cycle;

  //onchip_mem_s1_waits_for_write in a cycle, which is an e_mux
  assign onchip_mem_s1_waits_for_write = onchip_mem_s1_in_a_write_cycle & 0;

  //onchip_mem_s1_in_a_write_cycle assignment, which is an e_assign
  assign onchip_mem_s1_in_a_write_cycle = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = onchip_mem_s1_in_a_write_cycle;

  assign wait_for_onchip_mem_s1_counter = 0;
  //onchip_mem_s1_byteenable byte enable port mux, which is an e_mux
  assign onchip_mem_s1_byteenable = (cpu_data_master_granted_onchip_mem_s1)? cpu_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //onchip_mem/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_onchip_mem_s1 + cpu_instruction_master_granted_onchip_mem_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_onchip_mem_s1 + cpu_instruction_master_saved_grant_onchip_mem_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module pll_pll_slave_arbitrator (
                                  // inputs:
                                   clk,
                                   nios_sd_card_clock_0_out_address_to_slave,
                                   nios_sd_card_clock_0_out_read,
                                   nios_sd_card_clock_0_out_write,
                                   nios_sd_card_clock_0_out_writedata,
                                   pll_pll_slave_readdata,
                                   reset_n,

                                  // outputs:
                                   d1_pll_pll_slave_end_xfer,
                                   nios_sd_card_clock_0_out_granted_pll_pll_slave,
                                   nios_sd_card_clock_0_out_qualified_request_pll_pll_slave,
                                   nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave,
                                   nios_sd_card_clock_0_out_requests_pll_pll_slave,
                                   pll_pll_slave_address,
                                   pll_pll_slave_read,
                                   pll_pll_slave_readdata_from_sa,
                                   pll_pll_slave_reset,
                                   pll_pll_slave_write,
                                   pll_pll_slave_writedata
                                )
;

  output           d1_pll_pll_slave_end_xfer;
  output           nios_sd_card_clock_0_out_granted_pll_pll_slave;
  output           nios_sd_card_clock_0_out_qualified_request_pll_pll_slave;
  output           nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave;
  output           nios_sd_card_clock_0_out_requests_pll_pll_slave;
  output  [  1: 0] pll_pll_slave_address;
  output           pll_pll_slave_read;
  output  [ 31: 0] pll_pll_slave_readdata_from_sa;
  output           pll_pll_slave_reset;
  output           pll_pll_slave_write;
  output  [ 31: 0] pll_pll_slave_writedata;
  input            clk;
  input   [  3: 0] nios_sd_card_clock_0_out_address_to_slave;
  input            nios_sd_card_clock_0_out_read;
  input            nios_sd_card_clock_0_out_write;
  input   [ 31: 0] nios_sd_card_clock_0_out_writedata;
  input   [ 31: 0] pll_pll_slave_readdata;
  input            reset_n;

  reg              d1_pll_pll_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_pll_pll_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             nios_sd_card_clock_0_out_arbiterlock;
  wire             nios_sd_card_clock_0_out_arbiterlock2;
  wire             nios_sd_card_clock_0_out_continuerequest;
  wire             nios_sd_card_clock_0_out_granted_pll_pll_slave;
  wire             nios_sd_card_clock_0_out_qualified_request_pll_pll_slave;
  wire             nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave;
  wire             nios_sd_card_clock_0_out_requests_pll_pll_slave;
  wire             nios_sd_card_clock_0_out_saved_grant_pll_pll_slave;
  wire    [  1: 0] pll_pll_slave_address;
  wire             pll_pll_slave_allgrants;
  wire             pll_pll_slave_allow_new_arb_cycle;
  wire             pll_pll_slave_any_bursting_master_saved_grant;
  wire             pll_pll_slave_any_continuerequest;
  wire             pll_pll_slave_arb_counter_enable;
  reg              pll_pll_slave_arb_share_counter;
  wire             pll_pll_slave_arb_share_counter_next_value;
  wire             pll_pll_slave_arb_share_set_values;
  wire             pll_pll_slave_beginbursttransfer_internal;
  wire             pll_pll_slave_begins_xfer;
  wire             pll_pll_slave_end_xfer;
  wire             pll_pll_slave_firsttransfer;
  wire             pll_pll_slave_grant_vector;
  wire             pll_pll_slave_in_a_read_cycle;
  wire             pll_pll_slave_in_a_write_cycle;
  wire             pll_pll_slave_master_qreq_vector;
  wire             pll_pll_slave_non_bursting_master_requests;
  wire             pll_pll_slave_read;
  wire    [ 31: 0] pll_pll_slave_readdata_from_sa;
  reg              pll_pll_slave_reg_firsttransfer;
  wire             pll_pll_slave_reset;
  reg              pll_pll_slave_slavearbiterlockenable;
  wire             pll_pll_slave_slavearbiterlockenable2;
  wire             pll_pll_slave_unreg_firsttransfer;
  wire             pll_pll_slave_waits_for_read;
  wire             pll_pll_slave_waits_for_write;
  wire             pll_pll_slave_write;
  wire    [ 31: 0] pll_pll_slave_writedata;
  wire    [  3: 0] shifted_address_to_pll_pll_slave_from_nios_sd_card_clock_0_out;
  wire             wait_for_pll_pll_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~pll_pll_slave_end_xfer;
    end


  assign pll_pll_slave_begins_xfer = ~d1_reasons_to_wait & ((nios_sd_card_clock_0_out_qualified_request_pll_pll_slave));
  //assign pll_pll_slave_readdata_from_sa = pll_pll_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign pll_pll_slave_readdata_from_sa = pll_pll_slave_readdata;

  assign nios_sd_card_clock_0_out_requests_pll_pll_slave = (1) & (nios_sd_card_clock_0_out_read | nios_sd_card_clock_0_out_write);
  //pll_pll_slave_arb_share_counter set values, which is an e_mux
  assign pll_pll_slave_arb_share_set_values = 1;

  //pll_pll_slave_non_bursting_master_requests mux, which is an e_mux
  assign pll_pll_slave_non_bursting_master_requests = nios_sd_card_clock_0_out_requests_pll_pll_slave;

  //pll_pll_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign pll_pll_slave_any_bursting_master_saved_grant = 0;

  //pll_pll_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign pll_pll_slave_arb_share_counter_next_value = pll_pll_slave_firsttransfer ? (pll_pll_slave_arb_share_set_values - 1) : |pll_pll_slave_arb_share_counter ? (pll_pll_slave_arb_share_counter - 1) : 0;

  //pll_pll_slave_allgrants all slave grants, which is an e_mux
  assign pll_pll_slave_allgrants = |pll_pll_slave_grant_vector;

  //pll_pll_slave_end_xfer assignment, which is an e_assign
  assign pll_pll_slave_end_xfer = ~(pll_pll_slave_waits_for_read | pll_pll_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_pll_pll_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_pll_pll_slave = pll_pll_slave_end_xfer & (~pll_pll_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //pll_pll_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign pll_pll_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_pll_pll_slave & pll_pll_slave_allgrants) | (end_xfer_arb_share_counter_term_pll_pll_slave & ~pll_pll_slave_non_bursting_master_requests);

  //pll_pll_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          pll_pll_slave_arb_share_counter <= 0;
      else if (pll_pll_slave_arb_counter_enable)
          pll_pll_slave_arb_share_counter <= pll_pll_slave_arb_share_counter_next_value;
    end


  //pll_pll_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          pll_pll_slave_slavearbiterlockenable <= 0;
      else if ((|pll_pll_slave_master_qreq_vector & end_xfer_arb_share_counter_term_pll_pll_slave) | (end_xfer_arb_share_counter_term_pll_pll_slave & ~pll_pll_slave_non_bursting_master_requests))
          pll_pll_slave_slavearbiterlockenable <= |pll_pll_slave_arb_share_counter_next_value;
    end


  //nios_sd_card_clock_0/out pll/pll_slave arbiterlock, which is an e_assign
  assign nios_sd_card_clock_0_out_arbiterlock = pll_pll_slave_slavearbiterlockenable & nios_sd_card_clock_0_out_continuerequest;

  //pll_pll_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign pll_pll_slave_slavearbiterlockenable2 = |pll_pll_slave_arb_share_counter_next_value;

  //nios_sd_card_clock_0/out pll/pll_slave arbiterlock2, which is an e_assign
  assign nios_sd_card_clock_0_out_arbiterlock2 = pll_pll_slave_slavearbiterlockenable2 & nios_sd_card_clock_0_out_continuerequest;

  //pll_pll_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign pll_pll_slave_any_continuerequest = 1;

  //nios_sd_card_clock_0_out_continuerequest continued request, which is an e_assign
  assign nios_sd_card_clock_0_out_continuerequest = 1;

  assign nios_sd_card_clock_0_out_qualified_request_pll_pll_slave = nios_sd_card_clock_0_out_requests_pll_pll_slave;
  //pll_pll_slave_writedata mux, which is an e_mux
  assign pll_pll_slave_writedata = nios_sd_card_clock_0_out_writedata;

  //master is always granted when requested
  assign nios_sd_card_clock_0_out_granted_pll_pll_slave = nios_sd_card_clock_0_out_qualified_request_pll_pll_slave;

  //nios_sd_card_clock_0/out saved-grant pll/pll_slave, which is an e_assign
  assign nios_sd_card_clock_0_out_saved_grant_pll_pll_slave = nios_sd_card_clock_0_out_requests_pll_pll_slave;

  //allow new arb cycle for pll/pll_slave, which is an e_assign
  assign pll_pll_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign pll_pll_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign pll_pll_slave_master_qreq_vector = 1;

  //~pll_pll_slave_reset assignment, which is an e_assign
  assign pll_pll_slave_reset = ~reset_n;

  //pll_pll_slave_firsttransfer first transaction, which is an e_assign
  assign pll_pll_slave_firsttransfer = pll_pll_slave_begins_xfer ? pll_pll_slave_unreg_firsttransfer : pll_pll_slave_reg_firsttransfer;

  //pll_pll_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign pll_pll_slave_unreg_firsttransfer = ~(pll_pll_slave_slavearbiterlockenable & pll_pll_slave_any_continuerequest);

  //pll_pll_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          pll_pll_slave_reg_firsttransfer <= 1'b1;
      else if (pll_pll_slave_begins_xfer)
          pll_pll_slave_reg_firsttransfer <= pll_pll_slave_unreg_firsttransfer;
    end


  //pll_pll_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign pll_pll_slave_beginbursttransfer_internal = pll_pll_slave_begins_xfer;

  //pll_pll_slave_read assignment, which is an e_mux
  assign pll_pll_slave_read = nios_sd_card_clock_0_out_granted_pll_pll_slave & nios_sd_card_clock_0_out_read;

  //pll_pll_slave_write assignment, which is an e_mux
  assign pll_pll_slave_write = nios_sd_card_clock_0_out_granted_pll_pll_slave & nios_sd_card_clock_0_out_write;

  assign shifted_address_to_pll_pll_slave_from_nios_sd_card_clock_0_out = nios_sd_card_clock_0_out_address_to_slave;
  //pll_pll_slave_address mux, which is an e_mux
  assign pll_pll_slave_address = shifted_address_to_pll_pll_slave_from_nios_sd_card_clock_0_out >> 2;

  //d1_pll_pll_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_pll_pll_slave_end_xfer <= 1;
      else 
        d1_pll_pll_slave_end_xfer <= pll_pll_slave_end_xfer;
    end


  //pll_pll_slave_waits_for_read in a cycle, which is an e_mux
  assign pll_pll_slave_waits_for_read = pll_pll_slave_in_a_read_cycle & 0;

  //pll_pll_slave_in_a_read_cycle assignment, which is an e_assign
  assign pll_pll_slave_in_a_read_cycle = nios_sd_card_clock_0_out_granted_pll_pll_slave & nios_sd_card_clock_0_out_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = pll_pll_slave_in_a_read_cycle;

  //pll_pll_slave_waits_for_write in a cycle, which is an e_mux
  assign pll_pll_slave_waits_for_write = pll_pll_slave_in_a_write_cycle & 0;

  //pll_pll_slave_in_a_write_cycle assignment, which is an e_assign
  assign pll_pll_slave_in_a_write_cycle = nios_sd_card_clock_0_out_granted_pll_pll_slave & nios_sd_card_clock_0_out_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = pll_pll_slave_in_a_write_cycle;

  assign wait_for_pll_pll_slave_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //pll/pll_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sd_card_cpu_ctrl_arbitrator (
                                     // inputs:
                                      clk,
                                      cpu_data_master_address_to_slave,
                                      cpu_data_master_latency_counter,
                                      cpu_data_master_read,
                                      cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                      cpu_data_master_write,
                                      cpu_data_master_writedata,
                                      reset_n,
                                      sd_card_cpu_ctrl_readdata,

                                     // outputs:
                                      cpu_data_master_granted_sd_card_cpu_ctrl,
                                      cpu_data_master_qualified_request_sd_card_cpu_ctrl,
                                      cpu_data_master_read_data_valid_sd_card_cpu_ctrl,
                                      cpu_data_master_requests_sd_card_cpu_ctrl,
                                      d1_sd_card_cpu_ctrl_end_xfer,
                                      sd_card_cpu_ctrl_address,
                                      sd_card_cpu_ctrl_chipselect,
                                      sd_card_cpu_ctrl_readdata_from_sa,
                                      sd_card_cpu_ctrl_reset,
                                      sd_card_cpu_ctrl_write,
                                      sd_card_cpu_ctrl_writedata
                                   )
;

  output           cpu_data_master_granted_sd_card_cpu_ctrl;
  output           cpu_data_master_qualified_request_sd_card_cpu_ctrl;
  output           cpu_data_master_read_data_valid_sd_card_cpu_ctrl;
  output           cpu_data_master_requests_sd_card_cpu_ctrl;
  output           d1_sd_card_cpu_ctrl_end_xfer;
  output  [  1: 0] sd_card_cpu_ctrl_address;
  output           sd_card_cpu_ctrl_chipselect;
  output  [ 31: 0] sd_card_cpu_ctrl_readdata_from_sa;
  output           sd_card_cpu_ctrl_reset;
  output           sd_card_cpu_ctrl_write;
  output  [ 31: 0] sd_card_cpu_ctrl_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] sd_card_cpu_ctrl_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sd_card_cpu_ctrl;
  wire             cpu_data_master_qualified_request_sd_card_cpu_ctrl;
  wire             cpu_data_master_read_data_valid_sd_card_cpu_ctrl;
  wire             cpu_data_master_requests_sd_card_cpu_ctrl;
  wire             cpu_data_master_saved_grant_sd_card_cpu_ctrl;
  reg              d1_reasons_to_wait;
  reg              d1_sd_card_cpu_ctrl_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sd_card_cpu_ctrl;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] sd_card_cpu_ctrl_address;
  wire             sd_card_cpu_ctrl_allgrants;
  wire             sd_card_cpu_ctrl_allow_new_arb_cycle;
  wire             sd_card_cpu_ctrl_any_bursting_master_saved_grant;
  wire             sd_card_cpu_ctrl_any_continuerequest;
  wire             sd_card_cpu_ctrl_arb_counter_enable;
  reg     [  1: 0] sd_card_cpu_ctrl_arb_share_counter;
  wire    [  1: 0] sd_card_cpu_ctrl_arb_share_counter_next_value;
  wire    [  1: 0] sd_card_cpu_ctrl_arb_share_set_values;
  wire             sd_card_cpu_ctrl_beginbursttransfer_internal;
  wire             sd_card_cpu_ctrl_begins_xfer;
  wire             sd_card_cpu_ctrl_chipselect;
  wire             sd_card_cpu_ctrl_end_xfer;
  wire             sd_card_cpu_ctrl_firsttransfer;
  wire             sd_card_cpu_ctrl_grant_vector;
  wire             sd_card_cpu_ctrl_in_a_read_cycle;
  wire             sd_card_cpu_ctrl_in_a_write_cycle;
  wire             sd_card_cpu_ctrl_master_qreq_vector;
  wire             sd_card_cpu_ctrl_non_bursting_master_requests;
  wire    [ 31: 0] sd_card_cpu_ctrl_readdata_from_sa;
  reg              sd_card_cpu_ctrl_reg_firsttransfer;
  wire             sd_card_cpu_ctrl_reset;
  reg              sd_card_cpu_ctrl_slavearbiterlockenable;
  wire             sd_card_cpu_ctrl_slavearbiterlockenable2;
  wire             sd_card_cpu_ctrl_unreg_firsttransfer;
  wire             sd_card_cpu_ctrl_waits_for_read;
  wire             sd_card_cpu_ctrl_waits_for_write;
  wire             sd_card_cpu_ctrl_write;
  wire    [ 31: 0] sd_card_cpu_ctrl_writedata;
  wire    [ 24: 0] shifted_address_to_sd_card_cpu_ctrl_from_cpu_data_master;
  wire             wait_for_sd_card_cpu_ctrl_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sd_card_cpu_ctrl_end_xfer;
    end


  assign sd_card_cpu_ctrl_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sd_card_cpu_ctrl));
  //assign sd_card_cpu_ctrl_readdata_from_sa = sd_card_cpu_ctrl_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sd_card_cpu_ctrl_readdata_from_sa = sd_card_cpu_ctrl_readdata;

  assign cpu_data_master_requests_sd_card_cpu_ctrl = ({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h11090a0) & (cpu_data_master_read | cpu_data_master_write);
  //sd_card_cpu_ctrl_arb_share_counter set values, which is an e_mux
  assign sd_card_cpu_ctrl_arb_share_set_values = 1;

  //sd_card_cpu_ctrl_non_bursting_master_requests mux, which is an e_mux
  assign sd_card_cpu_ctrl_non_bursting_master_requests = cpu_data_master_requests_sd_card_cpu_ctrl;

  //sd_card_cpu_ctrl_any_bursting_master_saved_grant mux, which is an e_mux
  assign sd_card_cpu_ctrl_any_bursting_master_saved_grant = 0;

  //sd_card_cpu_ctrl_arb_share_counter_next_value assignment, which is an e_assign
  assign sd_card_cpu_ctrl_arb_share_counter_next_value = sd_card_cpu_ctrl_firsttransfer ? (sd_card_cpu_ctrl_arb_share_set_values - 1) : |sd_card_cpu_ctrl_arb_share_counter ? (sd_card_cpu_ctrl_arb_share_counter - 1) : 0;

  //sd_card_cpu_ctrl_allgrants all slave grants, which is an e_mux
  assign sd_card_cpu_ctrl_allgrants = |sd_card_cpu_ctrl_grant_vector;

  //sd_card_cpu_ctrl_end_xfer assignment, which is an e_assign
  assign sd_card_cpu_ctrl_end_xfer = ~(sd_card_cpu_ctrl_waits_for_read | sd_card_cpu_ctrl_waits_for_write);

  //end_xfer_arb_share_counter_term_sd_card_cpu_ctrl arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sd_card_cpu_ctrl = sd_card_cpu_ctrl_end_xfer & (~sd_card_cpu_ctrl_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sd_card_cpu_ctrl_arb_share_counter arbitration counter enable, which is an e_assign
  assign sd_card_cpu_ctrl_arb_counter_enable = (end_xfer_arb_share_counter_term_sd_card_cpu_ctrl & sd_card_cpu_ctrl_allgrants) | (end_xfer_arb_share_counter_term_sd_card_cpu_ctrl & ~sd_card_cpu_ctrl_non_bursting_master_requests);

  //sd_card_cpu_ctrl_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sd_card_cpu_ctrl_arb_share_counter <= 0;
      else if (sd_card_cpu_ctrl_arb_counter_enable)
          sd_card_cpu_ctrl_arb_share_counter <= sd_card_cpu_ctrl_arb_share_counter_next_value;
    end


  //sd_card_cpu_ctrl_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sd_card_cpu_ctrl_slavearbiterlockenable <= 0;
      else if ((|sd_card_cpu_ctrl_master_qreq_vector & end_xfer_arb_share_counter_term_sd_card_cpu_ctrl) | (end_xfer_arb_share_counter_term_sd_card_cpu_ctrl & ~sd_card_cpu_ctrl_non_bursting_master_requests))
          sd_card_cpu_ctrl_slavearbiterlockenable <= |sd_card_cpu_ctrl_arb_share_counter_next_value;
    end


  //cpu/data_master sd_card/cpu_ctrl arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sd_card_cpu_ctrl_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sd_card_cpu_ctrl_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sd_card_cpu_ctrl_slavearbiterlockenable2 = |sd_card_cpu_ctrl_arb_share_counter_next_value;

  //cpu/data_master sd_card/cpu_ctrl arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sd_card_cpu_ctrl_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //sd_card_cpu_ctrl_any_continuerequest at least one master continues requesting, which is an e_assign
  assign sd_card_cpu_ctrl_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_sd_card_cpu_ctrl = cpu_data_master_requests_sd_card_cpu_ctrl & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_sd_card_cpu_ctrl, which is an e_mux
  assign cpu_data_master_read_data_valid_sd_card_cpu_ctrl = cpu_data_master_granted_sd_card_cpu_ctrl & cpu_data_master_read & ~sd_card_cpu_ctrl_waits_for_read;

  //sd_card_cpu_ctrl_writedata mux, which is an e_mux
  assign sd_card_cpu_ctrl_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_sd_card_cpu_ctrl = cpu_data_master_qualified_request_sd_card_cpu_ctrl;

  //cpu/data_master saved-grant sd_card/cpu_ctrl, which is an e_assign
  assign cpu_data_master_saved_grant_sd_card_cpu_ctrl = cpu_data_master_requests_sd_card_cpu_ctrl;

  //allow new arb cycle for sd_card/cpu_ctrl, which is an e_assign
  assign sd_card_cpu_ctrl_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign sd_card_cpu_ctrl_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign sd_card_cpu_ctrl_master_qreq_vector = 1;

  //~sd_card_cpu_ctrl_reset assignment, which is an e_assign
  assign sd_card_cpu_ctrl_reset = ~reset_n;

  assign sd_card_cpu_ctrl_chipselect = cpu_data_master_granted_sd_card_cpu_ctrl;
  //sd_card_cpu_ctrl_firsttransfer first transaction, which is an e_assign
  assign sd_card_cpu_ctrl_firsttransfer = sd_card_cpu_ctrl_begins_xfer ? sd_card_cpu_ctrl_unreg_firsttransfer : sd_card_cpu_ctrl_reg_firsttransfer;

  //sd_card_cpu_ctrl_unreg_firsttransfer first transaction, which is an e_assign
  assign sd_card_cpu_ctrl_unreg_firsttransfer = ~(sd_card_cpu_ctrl_slavearbiterlockenable & sd_card_cpu_ctrl_any_continuerequest);

  //sd_card_cpu_ctrl_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sd_card_cpu_ctrl_reg_firsttransfer <= 1'b1;
      else if (sd_card_cpu_ctrl_begins_xfer)
          sd_card_cpu_ctrl_reg_firsttransfer <= sd_card_cpu_ctrl_unreg_firsttransfer;
    end


  //sd_card_cpu_ctrl_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sd_card_cpu_ctrl_beginbursttransfer_internal = sd_card_cpu_ctrl_begins_xfer;

  //sd_card_cpu_ctrl_write assignment, which is an e_mux
  assign sd_card_cpu_ctrl_write = cpu_data_master_granted_sd_card_cpu_ctrl & cpu_data_master_write;

  assign shifted_address_to_sd_card_cpu_ctrl_from_cpu_data_master = cpu_data_master_address_to_slave;
  //sd_card_cpu_ctrl_address mux, which is an e_mux
  assign sd_card_cpu_ctrl_address = shifted_address_to_sd_card_cpu_ctrl_from_cpu_data_master >> 2;

  //d1_sd_card_cpu_ctrl_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sd_card_cpu_ctrl_end_xfer <= 1;
      else 
        d1_sd_card_cpu_ctrl_end_xfer <= sd_card_cpu_ctrl_end_xfer;
    end


  //sd_card_cpu_ctrl_waits_for_read in a cycle, which is an e_mux
  assign sd_card_cpu_ctrl_waits_for_read = sd_card_cpu_ctrl_in_a_read_cycle & sd_card_cpu_ctrl_begins_xfer;

  //sd_card_cpu_ctrl_in_a_read_cycle assignment, which is an e_assign
  assign sd_card_cpu_ctrl_in_a_read_cycle = cpu_data_master_granted_sd_card_cpu_ctrl & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sd_card_cpu_ctrl_in_a_read_cycle;

  //sd_card_cpu_ctrl_waits_for_write in a cycle, which is an e_mux
  assign sd_card_cpu_ctrl_waits_for_write = sd_card_cpu_ctrl_in_a_write_cycle & sd_card_cpu_ctrl_begins_xfer;

  //sd_card_cpu_ctrl_in_a_write_cycle assignment, which is an e_assign
  assign sd_card_cpu_ctrl_in_a_write_cycle = cpu_data_master_granted_sd_card_cpu_ctrl & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sd_card_cpu_ctrl_in_a_write_cycle;

  assign wait_for_sd_card_cpu_ctrl_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sd_card/cpu_ctrl enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_data_master_to_sdram_s1_module (
                                                         // inputs:
                                                          clear_fifo,
                                                          clk,
                                                          data_in,
                                                          read,
                                                          reset_n,
                                                          sync_reset,
                                                          write,

                                                         // outputs:
                                                          data_out,
                                                          empty,
                                                          fifo_contains_ones_n,
                                                          full
                                                       )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  wire             full_7;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_6;
  assign empty = !full_0;
  assign full_7 = 0;
  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    0;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module (
                                                                // inputs:
                                                                 clear_fifo,
                                                                 clk,
                                                                 data_in,
                                                                 read,
                                                                 reset_n,
                                                                 sync_reset,
                                                                 write,

                                                                // outputs:
                                                                 data_out,
                                                                 empty,
                                                                 fifo_contains_ones_n,
                                                                 full
                                                              )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  wire             full_7;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_6;
  assign empty = !full_0;
  assign full_7 = 0;
  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    0;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sdram_s1_arbitrator (
                             // inputs:
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_byteenable,
                              cpu_data_master_dbs_address,
                              cpu_data_master_dbs_write_16,
                              cpu_data_master_latency_counter,
                              cpu_data_master_read,
                              cpu_data_master_write,
                              cpu_instruction_master_address_to_slave,
                              cpu_instruction_master_dbs_address,
                              cpu_instruction_master_latency_counter,
                              cpu_instruction_master_read,
                              reset_n,
                              sdram_s1_readdata,
                              sdram_s1_readdatavalid,
                              sdram_s1_waitrequest,

                             // outputs:
                              cpu_data_master_byteenable_sdram_s1,
                              cpu_data_master_granted_sdram_s1,
                              cpu_data_master_qualified_request_sdram_s1,
                              cpu_data_master_read_data_valid_sdram_s1,
                              cpu_data_master_read_data_valid_sdram_s1_shift_register,
                              cpu_data_master_requests_sdram_s1,
                              cpu_instruction_master_granted_sdram_s1,
                              cpu_instruction_master_qualified_request_sdram_s1,
                              cpu_instruction_master_read_data_valid_sdram_s1,
                              cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                              cpu_instruction_master_requests_sdram_s1,
                              d1_sdram_s1_end_xfer,
                              sdram_s1_address,
                              sdram_s1_byteenable_n,
                              sdram_s1_chipselect,
                              sdram_s1_read_n,
                              sdram_s1_readdata_from_sa,
                              sdram_s1_reset_n,
                              sdram_s1_waitrequest_from_sa,
                              sdram_s1_write_n,
                              sdram_s1_writedata
                           )
;

  output  [  1: 0] cpu_data_master_byteenable_sdram_s1;
  output           cpu_data_master_granted_sdram_s1;
  output           cpu_data_master_qualified_request_sdram_s1;
  output           cpu_data_master_read_data_valid_sdram_s1;
  output           cpu_data_master_read_data_valid_sdram_s1_shift_register;
  output           cpu_data_master_requests_sdram_s1;
  output           cpu_instruction_master_granted_sdram_s1;
  output           cpu_instruction_master_qualified_request_sdram_s1;
  output           cpu_instruction_master_read_data_valid_sdram_s1;
  output           cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  output           cpu_instruction_master_requests_sdram_s1;
  output           d1_sdram_s1_end_xfer;
  output  [ 21: 0] sdram_s1_address;
  output  [  1: 0] sdram_s1_byteenable_n;
  output           sdram_s1_chipselect;
  output           sdram_s1_read_n;
  output  [ 15: 0] sdram_s1_readdata_from_sa;
  output           sdram_s1_reset_n;
  output           sdram_s1_waitrequest_from_sa;
  output           sdram_s1_write_n;
  output  [ 15: 0] sdram_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_dbs_address;
  input   [ 15: 0] cpu_data_master_dbs_write_16;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input   [ 24: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_dbs_address;
  input   [  1: 0] cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            reset_n;
  input   [ 15: 0] sdram_s1_readdata;
  input            sdram_s1_readdatavalid;
  input            sdram_s1_waitrequest;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1_segment_0;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1_segment_1;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sdram_s1;
  wire             cpu_data_master_qualified_request_sdram_s1;
  wire             cpu_data_master_rdv_fifo_empty_sdram_s1;
  wire             cpu_data_master_rdv_fifo_output_from_sdram_s1;
  wire             cpu_data_master_read_data_valid_sdram_s1;
  wire             cpu_data_master_read_data_valid_sdram_s1_shift_register;
  wire             cpu_data_master_requests_sdram_s1;
  wire             cpu_data_master_saved_grant_sdram_s1;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_sdram_s1;
  wire             cpu_instruction_master_qualified_request_sdram_s1;
  wire             cpu_instruction_master_rdv_fifo_empty_sdram_s1;
  wire             cpu_instruction_master_rdv_fifo_output_from_sdram_s1;
  wire             cpu_instruction_master_read_data_valid_sdram_s1;
  wire             cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  wire             cpu_instruction_master_requests_sdram_s1;
  wire             cpu_instruction_master_saved_grant_sdram_s1;
  reg              d1_reasons_to_wait;
  reg              d1_sdram_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sdram_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_sdram_s1;
  reg              last_cycle_cpu_instruction_master_granted_slave_sdram_s1;
  wire    [ 21: 0] sdram_s1_address;
  wire             sdram_s1_allgrants;
  wire             sdram_s1_allow_new_arb_cycle;
  wire             sdram_s1_any_bursting_master_saved_grant;
  wire             sdram_s1_any_continuerequest;
  reg     [  1: 0] sdram_s1_arb_addend;
  wire             sdram_s1_arb_counter_enable;
  reg     [  1: 0] sdram_s1_arb_share_counter;
  wire    [  1: 0] sdram_s1_arb_share_counter_next_value;
  wire    [  1: 0] sdram_s1_arb_share_set_values;
  wire    [  1: 0] sdram_s1_arb_winner;
  wire             sdram_s1_arbitration_holdoff_internal;
  wire             sdram_s1_beginbursttransfer_internal;
  wire             sdram_s1_begins_xfer;
  wire    [  1: 0] sdram_s1_byteenable_n;
  wire             sdram_s1_chipselect;
  wire    [  3: 0] sdram_s1_chosen_master_double_vector;
  wire    [  1: 0] sdram_s1_chosen_master_rot_left;
  wire             sdram_s1_end_xfer;
  wire             sdram_s1_firsttransfer;
  wire    [  1: 0] sdram_s1_grant_vector;
  wire             sdram_s1_in_a_read_cycle;
  wire             sdram_s1_in_a_write_cycle;
  wire    [  1: 0] sdram_s1_master_qreq_vector;
  wire             sdram_s1_move_on_to_next_transaction;
  wire             sdram_s1_non_bursting_master_requests;
  wire             sdram_s1_read_n;
  wire    [ 15: 0] sdram_s1_readdata_from_sa;
  wire             sdram_s1_readdatavalid_from_sa;
  reg              sdram_s1_reg_firsttransfer;
  wire             sdram_s1_reset_n;
  reg     [  1: 0] sdram_s1_saved_chosen_master_vector;
  reg              sdram_s1_slavearbiterlockenable;
  wire             sdram_s1_slavearbiterlockenable2;
  wire             sdram_s1_unreg_firsttransfer;
  wire             sdram_s1_waitrequest_from_sa;
  wire             sdram_s1_waits_for_read;
  wire             sdram_s1_waits_for_write;
  wire             sdram_s1_write_n;
  wire    [ 15: 0] sdram_s1_writedata;
  wire    [ 24: 0] shifted_address_to_sdram_s1_from_cpu_data_master;
  wire    [ 24: 0] shifted_address_to_sdram_s1_from_cpu_instruction_master;
  wire             wait_for_sdram_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sdram_s1_end_xfer;
    end


  assign sdram_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sdram_s1 | cpu_instruction_master_qualified_request_sdram_s1));
  //assign sdram_s1_readdatavalid_from_sa = sdram_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_s1_readdatavalid_from_sa = sdram_s1_readdatavalid;

  //assign sdram_s1_readdata_from_sa = sdram_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_s1_readdata_from_sa = sdram_s1_readdata;

  assign cpu_data_master_requests_sdram_s1 = ({cpu_data_master_address_to_slave[24 : 23] , 23'b0} == 25'h800000) & (cpu_data_master_read | cpu_data_master_write);
  //assign sdram_s1_waitrequest_from_sa = sdram_s1_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_s1_waitrequest_from_sa = sdram_s1_waitrequest;

  //sdram_s1_arb_share_counter set values, which is an e_mux
  assign sdram_s1_arb_share_set_values = (cpu_data_master_granted_sdram_s1)? 2 :
    (cpu_instruction_master_granted_sdram_s1)? 2 :
    (cpu_data_master_granted_sdram_s1)? 2 :
    (cpu_instruction_master_granted_sdram_s1)? 2 :
    1;

  //sdram_s1_non_bursting_master_requests mux, which is an e_mux
  assign sdram_s1_non_bursting_master_requests = cpu_data_master_requests_sdram_s1 |
    cpu_instruction_master_requests_sdram_s1 |
    cpu_data_master_requests_sdram_s1 |
    cpu_instruction_master_requests_sdram_s1;

  //sdram_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign sdram_s1_any_bursting_master_saved_grant = 0;

  //sdram_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign sdram_s1_arb_share_counter_next_value = sdram_s1_firsttransfer ? (sdram_s1_arb_share_set_values - 1) : |sdram_s1_arb_share_counter ? (sdram_s1_arb_share_counter - 1) : 0;

  //sdram_s1_allgrants all slave grants, which is an e_mux
  assign sdram_s1_allgrants = (|sdram_s1_grant_vector) |
    (|sdram_s1_grant_vector) |
    (|sdram_s1_grant_vector) |
    (|sdram_s1_grant_vector);

  //sdram_s1_end_xfer assignment, which is an e_assign
  assign sdram_s1_end_xfer = ~(sdram_s1_waits_for_read | sdram_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_sdram_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sdram_s1 = sdram_s1_end_xfer & (~sdram_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sdram_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign sdram_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_sdram_s1 & sdram_s1_allgrants) | (end_xfer_arb_share_counter_term_sdram_s1 & ~sdram_s1_non_bursting_master_requests);

  //sdram_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_arb_share_counter <= 0;
      else if (sdram_s1_arb_counter_enable)
          sdram_s1_arb_share_counter <= sdram_s1_arb_share_counter_next_value;
    end


  //sdram_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_slavearbiterlockenable <= 0;
      else if ((|sdram_s1_master_qreq_vector & end_xfer_arb_share_counter_term_sdram_s1) | (end_xfer_arb_share_counter_term_sdram_s1 & ~sdram_s1_non_bursting_master_requests))
          sdram_s1_slavearbiterlockenable <= |sdram_s1_arb_share_counter_next_value;
    end


  //cpu/data_master sdram/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sdram_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sdram_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sdram_s1_slavearbiterlockenable2 = |sdram_s1_arb_share_counter_next_value;

  //cpu/data_master sdram/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sdram_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master sdram/s1 arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = sdram_s1_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master sdram/s1 arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = sdram_s1_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted sdram/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_sdram_s1 <= 0;
      else 
        last_cycle_cpu_instruction_master_granted_slave_sdram_s1 <= cpu_instruction_master_saved_grant_sdram_s1 ? 1 : (sdram_s1_arbitration_holdoff_internal | ~cpu_instruction_master_requests_sdram_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_sdram_s1;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & cpu_instruction_master_requests_sdram_s1;

  //sdram_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign sdram_s1_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_sdram_s1 = cpu_data_master_requests_sdram_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (1 < cpu_data_master_latency_counter))) | ((!cpu_data_master_byteenable_sdram_s1) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //unique name for sdram_s1_move_on_to_next_transaction, which is an e_assign
  assign sdram_s1_move_on_to_next_transaction = sdram_s1_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_data_master_to_sdram_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_data_master_to_sdram_s1_module rdv_fifo_for_cpu_data_master_to_sdram_s1
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_data_master_granted_sdram_s1),
      .data_out             (cpu_data_master_rdv_fifo_output_from_sdram_s1),
      .empty                (),
      .fifo_contains_ones_n (cpu_data_master_rdv_fifo_empty_sdram_s1),
      .full                 (),
      .read                 (sdram_s1_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~sdram_s1_waits_for_read)
    );

  assign cpu_data_master_read_data_valid_sdram_s1_shift_register = ~cpu_data_master_rdv_fifo_empty_sdram_s1;
  //local readdatavalid cpu_data_master_read_data_valid_sdram_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_sdram_s1 = (sdram_s1_readdatavalid_from_sa & cpu_data_master_rdv_fifo_output_from_sdram_s1) & ~ cpu_data_master_rdv_fifo_empty_sdram_s1;

  //sdram_s1_writedata mux, which is an e_mux
  assign sdram_s1_writedata = cpu_data_master_dbs_write_16;

  assign cpu_instruction_master_requests_sdram_s1 = (({cpu_instruction_master_address_to_slave[24 : 23] , 23'b0} == 25'h800000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted sdram/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_sdram_s1 <= 0;
      else 
        last_cycle_cpu_data_master_granted_slave_sdram_s1 <= cpu_data_master_saved_grant_sdram_s1 ? 1 : (sdram_s1_arbitration_holdoff_internal | ~cpu_data_master_requests_sdram_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_sdram_s1;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_sdram_s1 & cpu_data_master_requests_sdram_s1;

  assign cpu_instruction_master_qualified_request_sdram_s1 = cpu_instruction_master_requests_sdram_s1 & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0) | (1 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock);
  //rdv_fifo_for_cpu_instruction_master_to_sdram_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module rdv_fifo_for_cpu_instruction_master_to_sdram_s1
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_instruction_master_granted_sdram_s1),
      .data_out             (cpu_instruction_master_rdv_fifo_output_from_sdram_s1),
      .empty                (),
      .fifo_contains_ones_n (cpu_instruction_master_rdv_fifo_empty_sdram_s1),
      .full                 (),
      .read                 (sdram_s1_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~sdram_s1_waits_for_read)
    );

  assign cpu_instruction_master_read_data_valid_sdram_s1_shift_register = ~cpu_instruction_master_rdv_fifo_empty_sdram_s1;
  //local readdatavalid cpu_instruction_master_read_data_valid_sdram_s1, which is an e_mux
  assign cpu_instruction_master_read_data_valid_sdram_s1 = (sdram_s1_readdatavalid_from_sa & cpu_instruction_master_rdv_fifo_output_from_sdram_s1) & ~ cpu_instruction_master_rdv_fifo_empty_sdram_s1;

  //allow new arb cycle for sdram/s1, which is an e_assign
  assign sdram_s1_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for sdram/s1, which is an e_assign
  assign sdram_s1_master_qreq_vector[0] = cpu_instruction_master_qualified_request_sdram_s1;

  //cpu/instruction_master grant sdram/s1, which is an e_assign
  assign cpu_instruction_master_granted_sdram_s1 = sdram_s1_grant_vector[0];

  //cpu/instruction_master saved-grant sdram/s1, which is an e_assign
  assign cpu_instruction_master_saved_grant_sdram_s1 = sdram_s1_arb_winner[0] && cpu_instruction_master_requests_sdram_s1;

  //cpu/data_master assignment into master qualified-requests vector for sdram/s1, which is an e_assign
  assign sdram_s1_master_qreq_vector[1] = cpu_data_master_qualified_request_sdram_s1;

  //cpu/data_master grant sdram/s1, which is an e_assign
  assign cpu_data_master_granted_sdram_s1 = sdram_s1_grant_vector[1];

  //cpu/data_master saved-grant sdram/s1, which is an e_assign
  assign cpu_data_master_saved_grant_sdram_s1 = sdram_s1_arb_winner[1] && cpu_data_master_requests_sdram_s1;

  //sdram/s1 chosen-master double-vector, which is an e_assign
  assign sdram_s1_chosen_master_double_vector = {sdram_s1_master_qreq_vector, sdram_s1_master_qreq_vector} & ({~sdram_s1_master_qreq_vector, ~sdram_s1_master_qreq_vector} + sdram_s1_arb_addend);

  //stable onehot encoding of arb winner
  assign sdram_s1_arb_winner = (sdram_s1_allow_new_arb_cycle & | sdram_s1_grant_vector) ? sdram_s1_grant_vector : sdram_s1_saved_chosen_master_vector;

  //saved sdram_s1_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_saved_chosen_master_vector <= 0;
      else if (sdram_s1_allow_new_arb_cycle)
          sdram_s1_saved_chosen_master_vector <= |sdram_s1_grant_vector ? sdram_s1_grant_vector : sdram_s1_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign sdram_s1_grant_vector = {(sdram_s1_chosen_master_double_vector[1] | sdram_s1_chosen_master_double_vector[3]),
    (sdram_s1_chosen_master_double_vector[0] | sdram_s1_chosen_master_double_vector[2])};

  //sdram/s1 chosen master rotated left, which is an e_assign
  assign sdram_s1_chosen_master_rot_left = (sdram_s1_arb_winner << 1) ? (sdram_s1_arb_winner << 1) : 1;

  //sdram/s1's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_arb_addend <= 1;
      else if (|sdram_s1_grant_vector)
          sdram_s1_arb_addend <= sdram_s1_end_xfer? sdram_s1_chosen_master_rot_left : sdram_s1_grant_vector;
    end


  //sdram_s1_reset_n assignment, which is an e_assign
  assign sdram_s1_reset_n = reset_n;

  assign sdram_s1_chipselect = cpu_data_master_granted_sdram_s1 | cpu_instruction_master_granted_sdram_s1;
  //sdram_s1_firsttransfer first transaction, which is an e_assign
  assign sdram_s1_firsttransfer = sdram_s1_begins_xfer ? sdram_s1_unreg_firsttransfer : sdram_s1_reg_firsttransfer;

  //sdram_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign sdram_s1_unreg_firsttransfer = ~(sdram_s1_slavearbiterlockenable & sdram_s1_any_continuerequest);

  //sdram_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_reg_firsttransfer <= 1'b1;
      else if (sdram_s1_begins_xfer)
          sdram_s1_reg_firsttransfer <= sdram_s1_unreg_firsttransfer;
    end


  //sdram_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sdram_s1_beginbursttransfer_internal = sdram_s1_begins_xfer;

  //sdram_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign sdram_s1_arbitration_holdoff_internal = sdram_s1_begins_xfer & sdram_s1_firsttransfer;

  //~sdram_s1_read_n assignment, which is an e_mux
  assign sdram_s1_read_n = ~((cpu_data_master_granted_sdram_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_sdram_s1 & cpu_instruction_master_read));

  //~sdram_s1_write_n assignment, which is an e_mux
  assign sdram_s1_write_n = ~(cpu_data_master_granted_sdram_s1 & cpu_data_master_write);

  assign shifted_address_to_sdram_s1_from_cpu_data_master = {cpu_data_master_address_to_slave >> 2,
    cpu_data_master_dbs_address[1],
    {1 {1'b0}}};

  //sdram_s1_address mux, which is an e_mux
  assign sdram_s1_address = (cpu_data_master_granted_sdram_s1)? (shifted_address_to_sdram_s1_from_cpu_data_master >> 1) :
    (shifted_address_to_sdram_s1_from_cpu_instruction_master >> 1);

  assign shifted_address_to_sdram_s1_from_cpu_instruction_master = {cpu_instruction_master_address_to_slave >> 2,
    cpu_instruction_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_sdram_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sdram_s1_end_xfer <= 1;
      else 
        d1_sdram_s1_end_xfer <= sdram_s1_end_xfer;
    end


  //sdram_s1_waits_for_read in a cycle, which is an e_mux
  assign sdram_s1_waits_for_read = sdram_s1_in_a_read_cycle & sdram_s1_waitrequest_from_sa;

  //sdram_s1_in_a_read_cycle assignment, which is an e_assign
  assign sdram_s1_in_a_read_cycle = (cpu_data_master_granted_sdram_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_sdram_s1 & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sdram_s1_in_a_read_cycle;

  //sdram_s1_waits_for_write in a cycle, which is an e_mux
  assign sdram_s1_waits_for_write = sdram_s1_in_a_write_cycle & sdram_s1_waitrequest_from_sa;

  //sdram_s1_in_a_write_cycle assignment, which is an e_assign
  assign sdram_s1_in_a_write_cycle = cpu_data_master_granted_sdram_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sdram_s1_in_a_write_cycle;

  assign wait_for_sdram_s1_counter = 0;
  //~sdram_s1_byteenable_n byte enable port mux, which is an e_mux
  assign sdram_s1_byteenable_n = ~((cpu_data_master_granted_sdram_s1)? cpu_data_master_byteenable_sdram_s1 :
    -1);

  assign {cpu_data_master_byteenable_sdram_s1_segment_1,
cpu_data_master_byteenable_sdram_s1_segment_0} = cpu_data_master_byteenable;
  assign cpu_data_master_byteenable_sdram_s1 = ((cpu_data_master_dbs_address[1] == 0))? cpu_data_master_byteenable_sdram_s1_segment_0 :
    cpu_data_master_byteenable_sdram_s1_segment_1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sdram/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_sdram_s1 + cpu_instruction_master_granted_sdram_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_sdram_s1 + cpu_instruction_master_saved_grant_sdram_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sram_cpu_ctrl_arbitrator (
                                  // inputs:
                                   clk,
                                   cpu_data_master_address_to_slave,
                                   cpu_data_master_byteenable,
                                   cpu_data_master_dbs_address,
                                   cpu_data_master_dbs_write_16,
                                   cpu_data_master_latency_counter,
                                   cpu_data_master_read,
                                   cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                   cpu_data_master_write,
                                   cpu_instruction_master_address_to_slave,
                                   cpu_instruction_master_dbs_address,
                                   cpu_instruction_master_latency_counter,
                                   cpu_instruction_master_read,
                                   cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                   reset_n,
                                   sram_cpu_ctrl_readdata,

                                  // outputs:
                                   cpu_data_master_byteenable_sram_cpu_ctrl,
                                   cpu_data_master_granted_sram_cpu_ctrl,
                                   cpu_data_master_qualified_request_sram_cpu_ctrl,
                                   cpu_data_master_read_data_valid_sram_cpu_ctrl,
                                   cpu_data_master_requests_sram_cpu_ctrl,
                                   cpu_instruction_master_granted_sram_cpu_ctrl,
                                   cpu_instruction_master_qualified_request_sram_cpu_ctrl,
                                   cpu_instruction_master_read_data_valid_sram_cpu_ctrl,
                                   cpu_instruction_master_requests_sram_cpu_ctrl,
                                   d1_sram_cpu_ctrl_end_xfer,
                                   sram_cpu_ctrl_address,
                                   sram_cpu_ctrl_byteenable_n,
                                   sram_cpu_ctrl_chipselect_n,
                                   sram_cpu_ctrl_read_n,
                                   sram_cpu_ctrl_readdata_from_sa,
                                   sram_cpu_ctrl_reset,
                                   sram_cpu_ctrl_write_n,
                                   sram_cpu_ctrl_writedata
                                )
;

  output  [  1: 0] cpu_data_master_byteenable_sram_cpu_ctrl;
  output           cpu_data_master_granted_sram_cpu_ctrl;
  output           cpu_data_master_qualified_request_sram_cpu_ctrl;
  output           cpu_data_master_read_data_valid_sram_cpu_ctrl;
  output           cpu_data_master_requests_sram_cpu_ctrl;
  output           cpu_instruction_master_granted_sram_cpu_ctrl;
  output           cpu_instruction_master_qualified_request_sram_cpu_ctrl;
  output           cpu_instruction_master_read_data_valid_sram_cpu_ctrl;
  output           cpu_instruction_master_requests_sram_cpu_ctrl;
  output           d1_sram_cpu_ctrl_end_xfer;
  output  [ 17: 0] sram_cpu_ctrl_address;
  output  [  1: 0] sram_cpu_ctrl_byteenable_n;
  output           sram_cpu_ctrl_chipselect_n;
  output           sram_cpu_ctrl_read_n;
  output  [ 15: 0] sram_cpu_ctrl_readdata_from_sa;
  output           sram_cpu_ctrl_reset;
  output           sram_cpu_ctrl_write_n;
  output  [ 15: 0] sram_cpu_ctrl_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_dbs_address;
  input   [ 15: 0] cpu_data_master_dbs_write_16;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 24: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_dbs_address;
  input   [  1: 0] cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  input            reset_n;
  input   [ 15: 0] sram_cpu_ctrl_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire    [  1: 0] cpu_data_master_byteenable_sram_cpu_ctrl;
  wire    [  1: 0] cpu_data_master_byteenable_sram_cpu_ctrl_segment_0;
  wire    [  1: 0] cpu_data_master_byteenable_sram_cpu_ctrl_segment_1;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sram_cpu_ctrl;
  wire             cpu_data_master_qualified_request_sram_cpu_ctrl;
  wire             cpu_data_master_read_data_valid_sram_cpu_ctrl;
  reg     [  1: 0] cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register;
  wire             cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register_in;
  wire             cpu_data_master_requests_sram_cpu_ctrl;
  wire             cpu_data_master_saved_grant_sram_cpu_ctrl;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_sram_cpu_ctrl;
  wire             cpu_instruction_master_qualified_request_sram_cpu_ctrl;
  wire             cpu_instruction_master_read_data_valid_sram_cpu_ctrl;
  reg     [  1: 0] cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register;
  wire             cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register_in;
  wire             cpu_instruction_master_requests_sram_cpu_ctrl;
  wire             cpu_instruction_master_saved_grant_sram_cpu_ctrl;
  reg              d1_reasons_to_wait;
  reg              d1_sram_cpu_ctrl_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sram_cpu_ctrl;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_sram_cpu_ctrl;
  reg              last_cycle_cpu_instruction_master_granted_slave_sram_cpu_ctrl;
  wire    [  1: 0] p1_cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register;
  wire    [  1: 0] p1_cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register;
  wire    [ 24: 0] shifted_address_to_sram_cpu_ctrl_from_cpu_data_master;
  wire    [ 24: 0] shifted_address_to_sram_cpu_ctrl_from_cpu_instruction_master;
  wire    [ 17: 0] sram_cpu_ctrl_address;
  wire             sram_cpu_ctrl_allgrants;
  wire             sram_cpu_ctrl_allow_new_arb_cycle;
  wire             sram_cpu_ctrl_any_bursting_master_saved_grant;
  wire             sram_cpu_ctrl_any_continuerequest;
  reg     [  1: 0] sram_cpu_ctrl_arb_addend;
  wire             sram_cpu_ctrl_arb_counter_enable;
  reg     [  1: 0] sram_cpu_ctrl_arb_share_counter;
  wire    [  1: 0] sram_cpu_ctrl_arb_share_counter_next_value;
  wire    [  1: 0] sram_cpu_ctrl_arb_share_set_values;
  wire    [  1: 0] sram_cpu_ctrl_arb_winner;
  wire             sram_cpu_ctrl_arbitration_holdoff_internal;
  wire             sram_cpu_ctrl_beginbursttransfer_internal;
  wire             sram_cpu_ctrl_begins_xfer;
  wire    [  1: 0] sram_cpu_ctrl_byteenable_n;
  wire             sram_cpu_ctrl_chipselect_n;
  wire    [  3: 0] sram_cpu_ctrl_chosen_master_double_vector;
  wire    [  1: 0] sram_cpu_ctrl_chosen_master_rot_left;
  wire             sram_cpu_ctrl_end_xfer;
  wire             sram_cpu_ctrl_firsttransfer;
  wire    [  1: 0] sram_cpu_ctrl_grant_vector;
  wire             sram_cpu_ctrl_in_a_read_cycle;
  wire             sram_cpu_ctrl_in_a_write_cycle;
  wire    [  1: 0] sram_cpu_ctrl_master_qreq_vector;
  wire             sram_cpu_ctrl_non_bursting_master_requests;
  wire             sram_cpu_ctrl_read_n;
  wire    [ 15: 0] sram_cpu_ctrl_readdata_from_sa;
  reg              sram_cpu_ctrl_reg_firsttransfer;
  wire             sram_cpu_ctrl_reset;
  reg     [  1: 0] sram_cpu_ctrl_saved_chosen_master_vector;
  reg              sram_cpu_ctrl_slavearbiterlockenable;
  wire             sram_cpu_ctrl_slavearbiterlockenable2;
  wire             sram_cpu_ctrl_unreg_firsttransfer;
  wire             sram_cpu_ctrl_waits_for_read;
  wire             sram_cpu_ctrl_waits_for_write;
  wire             sram_cpu_ctrl_write_n;
  wire    [ 15: 0] sram_cpu_ctrl_writedata;
  wire             wait_for_sram_cpu_ctrl_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sram_cpu_ctrl_end_xfer;
    end


  assign sram_cpu_ctrl_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sram_cpu_ctrl | cpu_instruction_master_qualified_request_sram_cpu_ctrl));
  //assign sram_cpu_ctrl_readdata_from_sa = sram_cpu_ctrl_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sram_cpu_ctrl_readdata_from_sa = sram_cpu_ctrl_readdata;

  assign cpu_data_master_requests_sram_cpu_ctrl = ({cpu_data_master_address_to_slave[24 : 19] , 19'b0} == 25'h100000) & (cpu_data_master_read | cpu_data_master_write);
  //sram_cpu_ctrl_arb_share_counter set values, which is an e_mux
  assign sram_cpu_ctrl_arb_share_set_values = (cpu_data_master_granted_sram_cpu_ctrl)? 2 :
    (cpu_instruction_master_granted_sram_cpu_ctrl)? 2 :
    (cpu_data_master_granted_sram_cpu_ctrl)? 2 :
    (cpu_instruction_master_granted_sram_cpu_ctrl)? 2 :
    1;

  //sram_cpu_ctrl_non_bursting_master_requests mux, which is an e_mux
  assign sram_cpu_ctrl_non_bursting_master_requests = cpu_data_master_requests_sram_cpu_ctrl |
    cpu_instruction_master_requests_sram_cpu_ctrl |
    cpu_data_master_requests_sram_cpu_ctrl |
    cpu_instruction_master_requests_sram_cpu_ctrl;

  //sram_cpu_ctrl_any_bursting_master_saved_grant mux, which is an e_mux
  assign sram_cpu_ctrl_any_bursting_master_saved_grant = 0;

  //sram_cpu_ctrl_arb_share_counter_next_value assignment, which is an e_assign
  assign sram_cpu_ctrl_arb_share_counter_next_value = sram_cpu_ctrl_firsttransfer ? (sram_cpu_ctrl_arb_share_set_values - 1) : |sram_cpu_ctrl_arb_share_counter ? (sram_cpu_ctrl_arb_share_counter - 1) : 0;

  //sram_cpu_ctrl_allgrants all slave grants, which is an e_mux
  assign sram_cpu_ctrl_allgrants = (|sram_cpu_ctrl_grant_vector) |
    (|sram_cpu_ctrl_grant_vector) |
    (|sram_cpu_ctrl_grant_vector) |
    (|sram_cpu_ctrl_grant_vector);

  //sram_cpu_ctrl_end_xfer assignment, which is an e_assign
  assign sram_cpu_ctrl_end_xfer = ~(sram_cpu_ctrl_waits_for_read | sram_cpu_ctrl_waits_for_write);

  //end_xfer_arb_share_counter_term_sram_cpu_ctrl arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sram_cpu_ctrl = sram_cpu_ctrl_end_xfer & (~sram_cpu_ctrl_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sram_cpu_ctrl_arb_share_counter arbitration counter enable, which is an e_assign
  assign sram_cpu_ctrl_arb_counter_enable = (end_xfer_arb_share_counter_term_sram_cpu_ctrl & sram_cpu_ctrl_allgrants) | (end_xfer_arb_share_counter_term_sram_cpu_ctrl & ~sram_cpu_ctrl_non_bursting_master_requests);

  //sram_cpu_ctrl_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_cpu_ctrl_arb_share_counter <= 0;
      else if (sram_cpu_ctrl_arb_counter_enable)
          sram_cpu_ctrl_arb_share_counter <= sram_cpu_ctrl_arb_share_counter_next_value;
    end


  //sram_cpu_ctrl_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_cpu_ctrl_slavearbiterlockenable <= 0;
      else if ((|sram_cpu_ctrl_master_qreq_vector & end_xfer_arb_share_counter_term_sram_cpu_ctrl) | (end_xfer_arb_share_counter_term_sram_cpu_ctrl & ~sram_cpu_ctrl_non_bursting_master_requests))
          sram_cpu_ctrl_slavearbiterlockenable <= |sram_cpu_ctrl_arb_share_counter_next_value;
    end


  //cpu/data_master sram/cpu_ctrl arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sram_cpu_ctrl_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sram_cpu_ctrl_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sram_cpu_ctrl_slavearbiterlockenable2 = |sram_cpu_ctrl_arb_share_counter_next_value;

  //cpu/data_master sram/cpu_ctrl arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sram_cpu_ctrl_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master sram/cpu_ctrl arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = sram_cpu_ctrl_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master sram/cpu_ctrl arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = sram_cpu_ctrl_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted sram/cpu_ctrl last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_sram_cpu_ctrl <= 0;
      else 
        last_cycle_cpu_instruction_master_granted_slave_sram_cpu_ctrl <= cpu_instruction_master_saved_grant_sram_cpu_ctrl ? 1 : (sram_cpu_ctrl_arbitration_holdoff_internal | ~cpu_instruction_master_requests_sram_cpu_ctrl) ? 0 : last_cycle_cpu_instruction_master_granted_slave_sram_cpu_ctrl;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_sram_cpu_ctrl & cpu_instruction_master_requests_sram_cpu_ctrl;

  //sram_cpu_ctrl_any_continuerequest at least one master continues requesting, which is an e_mux
  assign sram_cpu_ctrl_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_sram_cpu_ctrl = cpu_data_master_requests_sram_cpu_ctrl & ~((cpu_data_master_read & ((2 < cpu_data_master_latency_counter) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))) | ((!cpu_data_master_byteenable_sram_cpu_ctrl) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register_in = cpu_data_master_granted_sram_cpu_ctrl & cpu_data_master_read & ~sram_cpu_ctrl_waits_for_read;

  //shift register p1 cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register = {cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register, cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register_in};

  //cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register <= 0;
      else 
        cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register <= p1_cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register;
    end


  //local readdatavalid cpu_data_master_read_data_valid_sram_cpu_ctrl, which is an e_mux
  assign cpu_data_master_read_data_valid_sram_cpu_ctrl = cpu_data_master_read_data_valid_sram_cpu_ctrl_shift_register[1];

  //sram_cpu_ctrl_writedata mux, which is an e_mux
  assign sram_cpu_ctrl_writedata = cpu_data_master_dbs_write_16;

  assign cpu_instruction_master_requests_sram_cpu_ctrl = (({cpu_instruction_master_address_to_slave[24 : 19] , 19'b0} == 25'h100000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted sram/cpu_ctrl last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_sram_cpu_ctrl <= 0;
      else 
        last_cycle_cpu_data_master_granted_slave_sram_cpu_ctrl <= cpu_data_master_saved_grant_sram_cpu_ctrl ? 1 : (sram_cpu_ctrl_arbitration_holdoff_internal | ~cpu_data_master_requests_sram_cpu_ctrl) ? 0 : last_cycle_cpu_data_master_granted_slave_sram_cpu_ctrl;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_sram_cpu_ctrl & cpu_data_master_requests_sram_cpu_ctrl;

  assign cpu_instruction_master_qualified_request_sram_cpu_ctrl = cpu_instruction_master_requests_sram_cpu_ctrl & ~((cpu_instruction_master_read & ((2 < cpu_instruction_master_latency_counter) | (|cpu_instruction_master_read_data_valid_sdram_s1_shift_register))) | cpu_data_master_arbiterlock);
  //cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register_in = cpu_instruction_master_granted_sram_cpu_ctrl & cpu_instruction_master_read & ~sram_cpu_ctrl_waits_for_read;

  //shift register p1 cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register = {cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register, cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register_in};

  //cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register <= 0;
      else 
        cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register <= p1_cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register;
    end


  //local readdatavalid cpu_instruction_master_read_data_valid_sram_cpu_ctrl, which is an e_mux
  assign cpu_instruction_master_read_data_valid_sram_cpu_ctrl = cpu_instruction_master_read_data_valid_sram_cpu_ctrl_shift_register[1];

  //allow new arb cycle for sram/cpu_ctrl, which is an e_assign
  assign sram_cpu_ctrl_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for sram/cpu_ctrl, which is an e_assign
  assign sram_cpu_ctrl_master_qreq_vector[0] = cpu_instruction_master_qualified_request_sram_cpu_ctrl;

  //cpu/instruction_master grant sram/cpu_ctrl, which is an e_assign
  assign cpu_instruction_master_granted_sram_cpu_ctrl = sram_cpu_ctrl_grant_vector[0];

  //cpu/instruction_master saved-grant sram/cpu_ctrl, which is an e_assign
  assign cpu_instruction_master_saved_grant_sram_cpu_ctrl = sram_cpu_ctrl_arb_winner[0] && cpu_instruction_master_requests_sram_cpu_ctrl;

  //cpu/data_master assignment into master qualified-requests vector for sram/cpu_ctrl, which is an e_assign
  assign sram_cpu_ctrl_master_qreq_vector[1] = cpu_data_master_qualified_request_sram_cpu_ctrl;

  //cpu/data_master grant sram/cpu_ctrl, which is an e_assign
  assign cpu_data_master_granted_sram_cpu_ctrl = sram_cpu_ctrl_grant_vector[1];

  //cpu/data_master saved-grant sram/cpu_ctrl, which is an e_assign
  assign cpu_data_master_saved_grant_sram_cpu_ctrl = sram_cpu_ctrl_arb_winner[1] && cpu_data_master_requests_sram_cpu_ctrl;

  //sram/cpu_ctrl chosen-master double-vector, which is an e_assign
  assign sram_cpu_ctrl_chosen_master_double_vector = {sram_cpu_ctrl_master_qreq_vector, sram_cpu_ctrl_master_qreq_vector} & ({~sram_cpu_ctrl_master_qreq_vector, ~sram_cpu_ctrl_master_qreq_vector} + sram_cpu_ctrl_arb_addend);

  //stable onehot encoding of arb winner
  assign sram_cpu_ctrl_arb_winner = (sram_cpu_ctrl_allow_new_arb_cycle & | sram_cpu_ctrl_grant_vector) ? sram_cpu_ctrl_grant_vector : sram_cpu_ctrl_saved_chosen_master_vector;

  //saved sram_cpu_ctrl_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_cpu_ctrl_saved_chosen_master_vector <= 0;
      else if (sram_cpu_ctrl_allow_new_arb_cycle)
          sram_cpu_ctrl_saved_chosen_master_vector <= |sram_cpu_ctrl_grant_vector ? sram_cpu_ctrl_grant_vector : sram_cpu_ctrl_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign sram_cpu_ctrl_grant_vector = {(sram_cpu_ctrl_chosen_master_double_vector[1] | sram_cpu_ctrl_chosen_master_double_vector[3]),
    (sram_cpu_ctrl_chosen_master_double_vector[0] | sram_cpu_ctrl_chosen_master_double_vector[2])};

  //sram/cpu_ctrl chosen master rotated left, which is an e_assign
  assign sram_cpu_ctrl_chosen_master_rot_left = (sram_cpu_ctrl_arb_winner << 1) ? (sram_cpu_ctrl_arb_winner << 1) : 1;

  //sram/cpu_ctrl's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_cpu_ctrl_arb_addend <= 1;
      else if (|sram_cpu_ctrl_grant_vector)
          sram_cpu_ctrl_arb_addend <= sram_cpu_ctrl_end_xfer? sram_cpu_ctrl_chosen_master_rot_left : sram_cpu_ctrl_grant_vector;
    end


  //~sram_cpu_ctrl_reset assignment, which is an e_assign
  assign sram_cpu_ctrl_reset = ~reset_n;

  assign sram_cpu_ctrl_chipselect_n = ~(cpu_data_master_granted_sram_cpu_ctrl | cpu_instruction_master_granted_sram_cpu_ctrl);
  //sram_cpu_ctrl_firsttransfer first transaction, which is an e_assign
  assign sram_cpu_ctrl_firsttransfer = sram_cpu_ctrl_begins_xfer ? sram_cpu_ctrl_unreg_firsttransfer : sram_cpu_ctrl_reg_firsttransfer;

  //sram_cpu_ctrl_unreg_firsttransfer first transaction, which is an e_assign
  assign sram_cpu_ctrl_unreg_firsttransfer = ~(sram_cpu_ctrl_slavearbiterlockenable & sram_cpu_ctrl_any_continuerequest);

  //sram_cpu_ctrl_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_cpu_ctrl_reg_firsttransfer <= 1'b1;
      else if (sram_cpu_ctrl_begins_xfer)
          sram_cpu_ctrl_reg_firsttransfer <= sram_cpu_ctrl_unreg_firsttransfer;
    end


  //sram_cpu_ctrl_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sram_cpu_ctrl_beginbursttransfer_internal = sram_cpu_ctrl_begins_xfer;

  //sram_cpu_ctrl_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign sram_cpu_ctrl_arbitration_holdoff_internal = sram_cpu_ctrl_begins_xfer & sram_cpu_ctrl_firsttransfer;

  //~sram_cpu_ctrl_read_n assignment, which is an e_mux
  assign sram_cpu_ctrl_read_n = ~((cpu_data_master_granted_sram_cpu_ctrl & cpu_data_master_read) | (cpu_instruction_master_granted_sram_cpu_ctrl & cpu_instruction_master_read));

  //~sram_cpu_ctrl_write_n assignment, which is an e_mux
  assign sram_cpu_ctrl_write_n = ~(cpu_data_master_granted_sram_cpu_ctrl & cpu_data_master_write);

  assign shifted_address_to_sram_cpu_ctrl_from_cpu_data_master = {cpu_data_master_address_to_slave >> 2,
    cpu_data_master_dbs_address[1],
    {1 {1'b0}}};

  //sram_cpu_ctrl_address mux, which is an e_mux
  assign sram_cpu_ctrl_address = (cpu_data_master_granted_sram_cpu_ctrl)? (shifted_address_to_sram_cpu_ctrl_from_cpu_data_master >> 1) :
    (shifted_address_to_sram_cpu_ctrl_from_cpu_instruction_master >> 1);

  assign shifted_address_to_sram_cpu_ctrl_from_cpu_instruction_master = {cpu_instruction_master_address_to_slave >> 2,
    cpu_instruction_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_sram_cpu_ctrl_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sram_cpu_ctrl_end_xfer <= 1;
      else 
        d1_sram_cpu_ctrl_end_xfer <= sram_cpu_ctrl_end_xfer;
    end


  //sram_cpu_ctrl_waits_for_read in a cycle, which is an e_mux
  assign sram_cpu_ctrl_waits_for_read = sram_cpu_ctrl_in_a_read_cycle & 0;

  //sram_cpu_ctrl_in_a_read_cycle assignment, which is an e_assign
  assign sram_cpu_ctrl_in_a_read_cycle = (cpu_data_master_granted_sram_cpu_ctrl & cpu_data_master_read) | (cpu_instruction_master_granted_sram_cpu_ctrl & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sram_cpu_ctrl_in_a_read_cycle;

  //sram_cpu_ctrl_waits_for_write in a cycle, which is an e_mux
  assign sram_cpu_ctrl_waits_for_write = sram_cpu_ctrl_in_a_write_cycle & 0;

  //sram_cpu_ctrl_in_a_write_cycle assignment, which is an e_assign
  assign sram_cpu_ctrl_in_a_write_cycle = cpu_data_master_granted_sram_cpu_ctrl & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sram_cpu_ctrl_in_a_write_cycle;

  assign wait_for_sram_cpu_ctrl_counter = 0;
  //~sram_cpu_ctrl_byteenable_n byte enable port mux, which is an e_mux
  assign sram_cpu_ctrl_byteenable_n = ~((cpu_data_master_granted_sram_cpu_ctrl)? cpu_data_master_byteenable_sram_cpu_ctrl :
    -1);

  assign {cpu_data_master_byteenable_sram_cpu_ctrl_segment_1,
cpu_data_master_byteenable_sram_cpu_ctrl_segment_0} = cpu_data_master_byteenable;
  assign cpu_data_master_byteenable_sram_cpu_ctrl = ((cpu_data_master_dbs_address[1] == 0))? cpu_data_master_byteenable_sram_cpu_ctrl_segment_0 :
    cpu_data_master_byteenable_sram_cpu_ctrl_segment_1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sram/cpu_ctrl enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_sram_cpu_ctrl + cpu_instruction_master_granted_sram_cpu_ctrl > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_sram_cpu_ctrl + cpu_instruction_master_saved_grant_sram_cpu_ctrl > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sseg_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_latency_counter,
                             cpu_data_master_read,
                             cpu_data_master_read_data_valid_sdram_s1_shift_register,
                             cpu_data_master_write,
                             cpu_data_master_writedata,
                             reset_n,
                             sseg_s1_readdata,

                            // outputs:
                             cpu_data_master_granted_sseg_s1,
                             cpu_data_master_qualified_request_sseg_s1,
                             cpu_data_master_read_data_valid_sseg_s1,
                             cpu_data_master_requests_sseg_s1,
                             d1_sseg_s1_end_xfer,
                             sseg_s1_address,
                             sseg_s1_chipselect,
                             sseg_s1_readdata_from_sa,
                             sseg_s1_reset_n,
                             sseg_s1_write_n,
                             sseg_s1_writedata
                          )
;

  output           cpu_data_master_granted_sseg_s1;
  output           cpu_data_master_qualified_request_sseg_s1;
  output           cpu_data_master_read_data_valid_sseg_s1;
  output           cpu_data_master_requests_sseg_s1;
  output           d1_sseg_s1_end_xfer;
  output  [  1: 0] sseg_s1_address;
  output           sseg_s1_chipselect;
  output  [ 31: 0] sseg_s1_readdata_from_sa;
  output           sseg_s1_reset_n;
  output           sseg_s1_write_n;
  output  [ 31: 0] sseg_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] sseg_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sseg_s1;
  wire             cpu_data_master_qualified_request_sseg_s1;
  wire             cpu_data_master_read_data_valid_sseg_s1;
  wire             cpu_data_master_requests_sseg_s1;
  wire             cpu_data_master_saved_grant_sseg_s1;
  reg              d1_reasons_to_wait;
  reg              d1_sseg_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sseg_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_sseg_s1_from_cpu_data_master;
  wire    [  1: 0] sseg_s1_address;
  wire             sseg_s1_allgrants;
  wire             sseg_s1_allow_new_arb_cycle;
  wire             sseg_s1_any_bursting_master_saved_grant;
  wire             sseg_s1_any_continuerequest;
  wire             sseg_s1_arb_counter_enable;
  reg     [  1: 0] sseg_s1_arb_share_counter;
  wire    [  1: 0] sseg_s1_arb_share_counter_next_value;
  wire    [  1: 0] sseg_s1_arb_share_set_values;
  wire             sseg_s1_beginbursttransfer_internal;
  wire             sseg_s1_begins_xfer;
  wire             sseg_s1_chipselect;
  wire             sseg_s1_end_xfer;
  wire             sseg_s1_firsttransfer;
  wire             sseg_s1_grant_vector;
  wire             sseg_s1_in_a_read_cycle;
  wire             sseg_s1_in_a_write_cycle;
  wire             sseg_s1_master_qreq_vector;
  wire             sseg_s1_non_bursting_master_requests;
  wire    [ 31: 0] sseg_s1_readdata_from_sa;
  reg              sseg_s1_reg_firsttransfer;
  wire             sseg_s1_reset_n;
  reg              sseg_s1_slavearbiterlockenable;
  wire             sseg_s1_slavearbiterlockenable2;
  wire             sseg_s1_unreg_firsttransfer;
  wire             sseg_s1_waits_for_read;
  wire             sseg_s1_waits_for_write;
  wire             sseg_s1_write_n;
  wire    [ 31: 0] sseg_s1_writedata;
  wire             wait_for_sseg_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sseg_s1_end_xfer;
    end


  assign sseg_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sseg_s1));
  //assign sseg_s1_readdata_from_sa = sseg_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sseg_s1_readdata_from_sa = sseg_s1_readdata;

  assign cpu_data_master_requests_sseg_s1 = ({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1109060) & (cpu_data_master_read | cpu_data_master_write);
  //sseg_s1_arb_share_counter set values, which is an e_mux
  assign sseg_s1_arb_share_set_values = 1;

  //sseg_s1_non_bursting_master_requests mux, which is an e_mux
  assign sseg_s1_non_bursting_master_requests = cpu_data_master_requests_sseg_s1;

  //sseg_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign sseg_s1_any_bursting_master_saved_grant = 0;

  //sseg_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign sseg_s1_arb_share_counter_next_value = sseg_s1_firsttransfer ? (sseg_s1_arb_share_set_values - 1) : |sseg_s1_arb_share_counter ? (sseg_s1_arb_share_counter - 1) : 0;

  //sseg_s1_allgrants all slave grants, which is an e_mux
  assign sseg_s1_allgrants = |sseg_s1_grant_vector;

  //sseg_s1_end_xfer assignment, which is an e_assign
  assign sseg_s1_end_xfer = ~(sseg_s1_waits_for_read | sseg_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_sseg_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sseg_s1 = sseg_s1_end_xfer & (~sseg_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sseg_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign sseg_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_sseg_s1 & sseg_s1_allgrants) | (end_xfer_arb_share_counter_term_sseg_s1 & ~sseg_s1_non_bursting_master_requests);

  //sseg_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sseg_s1_arb_share_counter <= 0;
      else if (sseg_s1_arb_counter_enable)
          sseg_s1_arb_share_counter <= sseg_s1_arb_share_counter_next_value;
    end


  //sseg_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sseg_s1_slavearbiterlockenable <= 0;
      else if ((|sseg_s1_master_qreq_vector & end_xfer_arb_share_counter_term_sseg_s1) | (end_xfer_arb_share_counter_term_sseg_s1 & ~sseg_s1_non_bursting_master_requests))
          sseg_s1_slavearbiterlockenable <= |sseg_s1_arb_share_counter_next_value;
    end


  //cpu/data_master sseg/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sseg_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sseg_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sseg_s1_slavearbiterlockenable2 = |sseg_s1_arb_share_counter_next_value;

  //cpu/data_master sseg/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sseg_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //sseg_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign sseg_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_sseg_s1 = cpu_data_master_requests_sseg_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_sseg_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_sseg_s1 = cpu_data_master_granted_sseg_s1 & cpu_data_master_read & ~sseg_s1_waits_for_read;

  //sseg_s1_writedata mux, which is an e_mux
  assign sseg_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_sseg_s1 = cpu_data_master_qualified_request_sseg_s1;

  //cpu/data_master saved-grant sseg/s1, which is an e_assign
  assign cpu_data_master_saved_grant_sseg_s1 = cpu_data_master_requests_sseg_s1;

  //allow new arb cycle for sseg/s1, which is an e_assign
  assign sseg_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign sseg_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign sseg_s1_master_qreq_vector = 1;

  //sseg_s1_reset_n assignment, which is an e_assign
  assign sseg_s1_reset_n = reset_n;

  assign sseg_s1_chipselect = cpu_data_master_granted_sseg_s1;
  //sseg_s1_firsttransfer first transaction, which is an e_assign
  assign sseg_s1_firsttransfer = sseg_s1_begins_xfer ? sseg_s1_unreg_firsttransfer : sseg_s1_reg_firsttransfer;

  //sseg_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign sseg_s1_unreg_firsttransfer = ~(sseg_s1_slavearbiterlockenable & sseg_s1_any_continuerequest);

  //sseg_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sseg_s1_reg_firsttransfer <= 1'b1;
      else if (sseg_s1_begins_xfer)
          sseg_s1_reg_firsttransfer <= sseg_s1_unreg_firsttransfer;
    end


  //sseg_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sseg_s1_beginbursttransfer_internal = sseg_s1_begins_xfer;

  //~sseg_s1_write_n assignment, which is an e_mux
  assign sseg_s1_write_n = ~(cpu_data_master_granted_sseg_s1 & cpu_data_master_write);

  assign shifted_address_to_sseg_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //sseg_s1_address mux, which is an e_mux
  assign sseg_s1_address = shifted_address_to_sseg_s1_from_cpu_data_master >> 2;

  //d1_sseg_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sseg_s1_end_xfer <= 1;
      else 
        d1_sseg_s1_end_xfer <= sseg_s1_end_xfer;
    end


  //sseg_s1_waits_for_read in a cycle, which is an e_mux
  assign sseg_s1_waits_for_read = sseg_s1_in_a_read_cycle & sseg_s1_begins_xfer;

  //sseg_s1_in_a_read_cycle assignment, which is an e_assign
  assign sseg_s1_in_a_read_cycle = cpu_data_master_granted_sseg_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sseg_s1_in_a_read_cycle;

  //sseg_s1_waits_for_write in a cycle, which is an e_mux
  assign sseg_s1_waits_for_write = sseg_s1_in_a_write_cycle & 0;

  //sseg_s1_in_a_write_cycle assignment, which is an e_assign
  assign sseg_s1_in_a_write_cycle = cpu_data_master_granted_sseg_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sseg_s1_in_a_write_cycle;

  assign wait_for_sseg_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sseg/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module switch_s1_arbitrator (
                              // inputs:
                               clk,
                               cpu_data_master_address_to_slave,
                               cpu_data_master_latency_counter,
                               cpu_data_master_read,
                               cpu_data_master_read_data_valid_sdram_s1_shift_register,
                               cpu_data_master_write,
                               reset_n,
                               switch_s1_readdata,

                              // outputs:
                               cpu_data_master_granted_switch_s1,
                               cpu_data_master_qualified_request_switch_s1,
                               cpu_data_master_read_data_valid_switch_s1,
                               cpu_data_master_requests_switch_s1,
                               d1_switch_s1_end_xfer,
                               switch_s1_address,
                               switch_s1_readdata_from_sa,
                               switch_s1_reset_n
                            )
;

  output           cpu_data_master_granted_switch_s1;
  output           cpu_data_master_qualified_request_switch_s1;
  output           cpu_data_master_read_data_valid_switch_s1;
  output           cpu_data_master_requests_switch_s1;
  output           d1_switch_s1_end_xfer;
  output  [  1: 0] switch_s1_address;
  output  [ 31: 0] switch_s1_readdata_from_sa;
  output           switch_s1_reset_n;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input            reset_n;
  input   [ 31: 0] switch_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_switch_s1;
  wire             cpu_data_master_qualified_request_switch_s1;
  wire             cpu_data_master_read_data_valid_switch_s1;
  wire             cpu_data_master_requests_switch_s1;
  wire             cpu_data_master_saved_grant_switch_s1;
  reg              d1_reasons_to_wait;
  reg              d1_switch_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_switch_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_switch_s1_from_cpu_data_master;
  wire    [  1: 0] switch_s1_address;
  wire             switch_s1_allgrants;
  wire             switch_s1_allow_new_arb_cycle;
  wire             switch_s1_any_bursting_master_saved_grant;
  wire             switch_s1_any_continuerequest;
  wire             switch_s1_arb_counter_enable;
  reg     [  1: 0] switch_s1_arb_share_counter;
  wire    [  1: 0] switch_s1_arb_share_counter_next_value;
  wire    [  1: 0] switch_s1_arb_share_set_values;
  wire             switch_s1_beginbursttransfer_internal;
  wire             switch_s1_begins_xfer;
  wire             switch_s1_end_xfer;
  wire             switch_s1_firsttransfer;
  wire             switch_s1_grant_vector;
  wire             switch_s1_in_a_read_cycle;
  wire             switch_s1_in_a_write_cycle;
  wire             switch_s1_master_qreq_vector;
  wire             switch_s1_non_bursting_master_requests;
  wire    [ 31: 0] switch_s1_readdata_from_sa;
  reg              switch_s1_reg_firsttransfer;
  wire             switch_s1_reset_n;
  reg              switch_s1_slavearbiterlockenable;
  wire             switch_s1_slavearbiterlockenable2;
  wire             switch_s1_unreg_firsttransfer;
  wire             switch_s1_waits_for_read;
  wire             switch_s1_waits_for_write;
  wire             wait_for_switch_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~switch_s1_end_xfer;
    end


  assign switch_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_switch_s1));
  //assign switch_s1_readdata_from_sa = switch_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign switch_s1_readdata_from_sa = switch_s1_readdata;

  assign cpu_data_master_requests_switch_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1109070) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //switch_s1_arb_share_counter set values, which is an e_mux
  assign switch_s1_arb_share_set_values = 1;

  //switch_s1_non_bursting_master_requests mux, which is an e_mux
  assign switch_s1_non_bursting_master_requests = cpu_data_master_requests_switch_s1;

  //switch_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign switch_s1_any_bursting_master_saved_grant = 0;

  //switch_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign switch_s1_arb_share_counter_next_value = switch_s1_firsttransfer ? (switch_s1_arb_share_set_values - 1) : |switch_s1_arb_share_counter ? (switch_s1_arb_share_counter - 1) : 0;

  //switch_s1_allgrants all slave grants, which is an e_mux
  assign switch_s1_allgrants = |switch_s1_grant_vector;

  //switch_s1_end_xfer assignment, which is an e_assign
  assign switch_s1_end_xfer = ~(switch_s1_waits_for_read | switch_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_switch_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_switch_s1 = switch_s1_end_xfer & (~switch_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //switch_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign switch_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_switch_s1 & switch_s1_allgrants) | (end_xfer_arb_share_counter_term_switch_s1 & ~switch_s1_non_bursting_master_requests);

  //switch_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          switch_s1_arb_share_counter <= 0;
      else if (switch_s1_arb_counter_enable)
          switch_s1_arb_share_counter <= switch_s1_arb_share_counter_next_value;
    end


  //switch_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          switch_s1_slavearbiterlockenable <= 0;
      else if ((|switch_s1_master_qreq_vector & end_xfer_arb_share_counter_term_switch_s1) | (end_xfer_arb_share_counter_term_switch_s1 & ~switch_s1_non_bursting_master_requests))
          switch_s1_slavearbiterlockenable <= |switch_s1_arb_share_counter_next_value;
    end


  //cpu/data_master switch/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = switch_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //switch_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign switch_s1_slavearbiterlockenable2 = |switch_s1_arb_share_counter_next_value;

  //cpu/data_master switch/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = switch_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //switch_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign switch_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_switch_s1 = cpu_data_master_requests_switch_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_switch_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_switch_s1 = cpu_data_master_granted_switch_s1 & cpu_data_master_read & ~switch_s1_waits_for_read;

  //master is always granted when requested
  assign cpu_data_master_granted_switch_s1 = cpu_data_master_qualified_request_switch_s1;

  //cpu/data_master saved-grant switch/s1, which is an e_assign
  assign cpu_data_master_saved_grant_switch_s1 = cpu_data_master_requests_switch_s1;

  //allow new arb cycle for switch/s1, which is an e_assign
  assign switch_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign switch_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign switch_s1_master_qreq_vector = 1;

  //switch_s1_reset_n assignment, which is an e_assign
  assign switch_s1_reset_n = reset_n;

  //switch_s1_firsttransfer first transaction, which is an e_assign
  assign switch_s1_firsttransfer = switch_s1_begins_xfer ? switch_s1_unreg_firsttransfer : switch_s1_reg_firsttransfer;

  //switch_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign switch_s1_unreg_firsttransfer = ~(switch_s1_slavearbiterlockenable & switch_s1_any_continuerequest);

  //switch_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          switch_s1_reg_firsttransfer <= 1'b1;
      else if (switch_s1_begins_xfer)
          switch_s1_reg_firsttransfer <= switch_s1_unreg_firsttransfer;
    end


  //switch_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign switch_s1_beginbursttransfer_internal = switch_s1_begins_xfer;

  assign shifted_address_to_switch_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //switch_s1_address mux, which is an e_mux
  assign switch_s1_address = shifted_address_to_switch_s1_from_cpu_data_master >> 2;

  //d1_switch_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_switch_s1_end_xfer <= 1;
      else 
        d1_switch_s1_end_xfer <= switch_s1_end_xfer;
    end


  //switch_s1_waits_for_read in a cycle, which is an e_mux
  assign switch_s1_waits_for_read = switch_s1_in_a_read_cycle & switch_s1_begins_xfer;

  //switch_s1_in_a_read_cycle assignment, which is an e_assign
  assign switch_s1_in_a_read_cycle = cpu_data_master_granted_switch_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = switch_s1_in_a_read_cycle;

  //switch_s1_waits_for_write in a cycle, which is an e_mux
  assign switch_s1_waits_for_write = switch_s1_in_a_write_cycle & 0;

  //switch_s1_in_a_write_cycle assignment, which is an e_assign
  assign switch_s1_in_a_write_cycle = cpu_data_master_granted_switch_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = switch_s1_in_a_write_cycle;

  assign wait_for_switch_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //switch/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sys_timer_s1_arbitrator (
                                 // inputs:
                                  clk,
                                  cpu_data_master_address_to_slave,
                                  cpu_data_master_latency_counter,
                                  cpu_data_master_read,
                                  cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                  cpu_data_master_write,
                                  cpu_data_master_writedata,
                                  reset_n,
                                  sys_timer_s1_irq,
                                  sys_timer_s1_readdata,

                                 // outputs:
                                  cpu_data_master_granted_sys_timer_s1,
                                  cpu_data_master_qualified_request_sys_timer_s1,
                                  cpu_data_master_read_data_valid_sys_timer_s1,
                                  cpu_data_master_requests_sys_timer_s1,
                                  d1_sys_timer_s1_end_xfer,
                                  sys_timer_s1_address,
                                  sys_timer_s1_chipselect,
                                  sys_timer_s1_irq_from_sa,
                                  sys_timer_s1_readdata_from_sa,
                                  sys_timer_s1_reset_n,
                                  sys_timer_s1_write_n,
                                  sys_timer_s1_writedata
                               )
;

  output           cpu_data_master_granted_sys_timer_s1;
  output           cpu_data_master_qualified_request_sys_timer_s1;
  output           cpu_data_master_read_data_valid_sys_timer_s1;
  output           cpu_data_master_requests_sys_timer_s1;
  output           d1_sys_timer_s1_end_xfer;
  output  [  2: 0] sys_timer_s1_address;
  output           sys_timer_s1_chipselect;
  output           sys_timer_s1_irq_from_sa;
  output  [ 15: 0] sys_timer_s1_readdata_from_sa;
  output           sys_timer_s1_reset_n;
  output           sys_timer_s1_write_n;
  output  [ 15: 0] sys_timer_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input            sys_timer_s1_irq;
  input   [ 15: 0] sys_timer_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sys_timer_s1;
  wire             cpu_data_master_qualified_request_sys_timer_s1;
  wire             cpu_data_master_read_data_valid_sys_timer_s1;
  wire             cpu_data_master_requests_sys_timer_s1;
  wire             cpu_data_master_saved_grant_sys_timer_s1;
  reg              d1_reasons_to_wait;
  reg              d1_sys_timer_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sys_timer_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_sys_timer_s1_from_cpu_data_master;
  wire    [  2: 0] sys_timer_s1_address;
  wire             sys_timer_s1_allgrants;
  wire             sys_timer_s1_allow_new_arb_cycle;
  wire             sys_timer_s1_any_bursting_master_saved_grant;
  wire             sys_timer_s1_any_continuerequest;
  wire             sys_timer_s1_arb_counter_enable;
  reg     [  1: 0] sys_timer_s1_arb_share_counter;
  wire    [  1: 0] sys_timer_s1_arb_share_counter_next_value;
  wire    [  1: 0] sys_timer_s1_arb_share_set_values;
  wire             sys_timer_s1_beginbursttransfer_internal;
  wire             sys_timer_s1_begins_xfer;
  wire             sys_timer_s1_chipselect;
  wire             sys_timer_s1_end_xfer;
  wire             sys_timer_s1_firsttransfer;
  wire             sys_timer_s1_grant_vector;
  wire             sys_timer_s1_in_a_read_cycle;
  wire             sys_timer_s1_in_a_write_cycle;
  wire             sys_timer_s1_irq_from_sa;
  wire             sys_timer_s1_master_qreq_vector;
  wire             sys_timer_s1_non_bursting_master_requests;
  wire    [ 15: 0] sys_timer_s1_readdata_from_sa;
  reg              sys_timer_s1_reg_firsttransfer;
  wire             sys_timer_s1_reset_n;
  reg              sys_timer_s1_slavearbiterlockenable;
  wire             sys_timer_s1_slavearbiterlockenable2;
  wire             sys_timer_s1_unreg_firsttransfer;
  wire             sys_timer_s1_waits_for_read;
  wire             sys_timer_s1_waits_for_write;
  wire             sys_timer_s1_write_n;
  wire    [ 15: 0] sys_timer_s1_writedata;
  wire             wait_for_sys_timer_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sys_timer_s1_end_xfer;
    end


  assign sys_timer_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sys_timer_s1));
  //assign sys_timer_s1_readdata_from_sa = sys_timer_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sys_timer_s1_readdata_from_sa = sys_timer_s1_readdata;

  assign cpu_data_master_requests_sys_timer_s1 = ({cpu_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h1109000) & (cpu_data_master_read | cpu_data_master_write);
  //sys_timer_s1_arb_share_counter set values, which is an e_mux
  assign sys_timer_s1_arb_share_set_values = 1;

  //sys_timer_s1_non_bursting_master_requests mux, which is an e_mux
  assign sys_timer_s1_non_bursting_master_requests = cpu_data_master_requests_sys_timer_s1;

  //sys_timer_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign sys_timer_s1_any_bursting_master_saved_grant = 0;

  //sys_timer_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign sys_timer_s1_arb_share_counter_next_value = sys_timer_s1_firsttransfer ? (sys_timer_s1_arb_share_set_values - 1) : |sys_timer_s1_arb_share_counter ? (sys_timer_s1_arb_share_counter - 1) : 0;

  //sys_timer_s1_allgrants all slave grants, which is an e_mux
  assign sys_timer_s1_allgrants = |sys_timer_s1_grant_vector;

  //sys_timer_s1_end_xfer assignment, which is an e_assign
  assign sys_timer_s1_end_xfer = ~(sys_timer_s1_waits_for_read | sys_timer_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_sys_timer_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sys_timer_s1 = sys_timer_s1_end_xfer & (~sys_timer_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sys_timer_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign sys_timer_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_sys_timer_s1 & sys_timer_s1_allgrants) | (end_xfer_arb_share_counter_term_sys_timer_s1 & ~sys_timer_s1_non_bursting_master_requests);

  //sys_timer_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sys_timer_s1_arb_share_counter <= 0;
      else if (sys_timer_s1_arb_counter_enable)
          sys_timer_s1_arb_share_counter <= sys_timer_s1_arb_share_counter_next_value;
    end


  //sys_timer_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sys_timer_s1_slavearbiterlockenable <= 0;
      else if ((|sys_timer_s1_master_qreq_vector & end_xfer_arb_share_counter_term_sys_timer_s1) | (end_xfer_arb_share_counter_term_sys_timer_s1 & ~sys_timer_s1_non_bursting_master_requests))
          sys_timer_s1_slavearbiterlockenable <= |sys_timer_s1_arb_share_counter_next_value;
    end


  //cpu/data_master sys_timer/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sys_timer_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sys_timer_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sys_timer_s1_slavearbiterlockenable2 = |sys_timer_s1_arb_share_counter_next_value;

  //cpu/data_master sys_timer/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sys_timer_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //sys_timer_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign sys_timer_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_sys_timer_s1 = cpu_data_master_requests_sys_timer_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_sys_timer_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_sys_timer_s1 = cpu_data_master_granted_sys_timer_s1 & cpu_data_master_read & ~sys_timer_s1_waits_for_read;

  //sys_timer_s1_writedata mux, which is an e_mux
  assign sys_timer_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_sys_timer_s1 = cpu_data_master_qualified_request_sys_timer_s1;

  //cpu/data_master saved-grant sys_timer/s1, which is an e_assign
  assign cpu_data_master_saved_grant_sys_timer_s1 = cpu_data_master_requests_sys_timer_s1;

  //allow new arb cycle for sys_timer/s1, which is an e_assign
  assign sys_timer_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign sys_timer_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign sys_timer_s1_master_qreq_vector = 1;

  //sys_timer_s1_reset_n assignment, which is an e_assign
  assign sys_timer_s1_reset_n = reset_n;

  assign sys_timer_s1_chipselect = cpu_data_master_granted_sys_timer_s1;
  //sys_timer_s1_firsttransfer first transaction, which is an e_assign
  assign sys_timer_s1_firsttransfer = sys_timer_s1_begins_xfer ? sys_timer_s1_unreg_firsttransfer : sys_timer_s1_reg_firsttransfer;

  //sys_timer_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign sys_timer_s1_unreg_firsttransfer = ~(sys_timer_s1_slavearbiterlockenable & sys_timer_s1_any_continuerequest);

  //sys_timer_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sys_timer_s1_reg_firsttransfer <= 1'b1;
      else if (sys_timer_s1_begins_xfer)
          sys_timer_s1_reg_firsttransfer <= sys_timer_s1_unreg_firsttransfer;
    end


  //sys_timer_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sys_timer_s1_beginbursttransfer_internal = sys_timer_s1_begins_xfer;

  //~sys_timer_s1_write_n assignment, which is an e_mux
  assign sys_timer_s1_write_n = ~(cpu_data_master_granted_sys_timer_s1 & cpu_data_master_write);

  assign shifted_address_to_sys_timer_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //sys_timer_s1_address mux, which is an e_mux
  assign sys_timer_s1_address = shifted_address_to_sys_timer_s1_from_cpu_data_master >> 2;

  //d1_sys_timer_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sys_timer_s1_end_xfer <= 1;
      else 
        d1_sys_timer_s1_end_xfer <= sys_timer_s1_end_xfer;
    end


  //sys_timer_s1_waits_for_read in a cycle, which is an e_mux
  assign sys_timer_s1_waits_for_read = sys_timer_s1_in_a_read_cycle & sys_timer_s1_begins_xfer;

  //sys_timer_s1_in_a_read_cycle assignment, which is an e_assign
  assign sys_timer_s1_in_a_read_cycle = cpu_data_master_granted_sys_timer_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sys_timer_s1_in_a_read_cycle;

  //sys_timer_s1_waits_for_write in a cycle, which is an e_mux
  assign sys_timer_s1_waits_for_write = sys_timer_s1_in_a_write_cycle & 0;

  //sys_timer_s1_in_a_write_cycle assignment, which is an e_assign
  assign sys_timer_s1_in_a_write_cycle = cpu_data_master_granted_sys_timer_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sys_timer_s1_in_a_write_cycle;

  assign wait_for_sys_timer_s1_counter = 0;
  //assign sys_timer_s1_irq_from_sa = sys_timer_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sys_timer_s1_irq_from_sa = sys_timer_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sys_timer/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sysid_control_slave_arbitrator (
                                        // inputs:
                                         clk,
                                         cpu_data_master_address_to_slave,
                                         cpu_data_master_latency_counter,
                                         cpu_data_master_read,
                                         cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                         cpu_data_master_write,
                                         reset_n,
                                         sysid_control_slave_readdata,

                                        // outputs:
                                         cpu_data_master_granted_sysid_control_slave,
                                         cpu_data_master_qualified_request_sysid_control_slave,
                                         cpu_data_master_read_data_valid_sysid_control_slave,
                                         cpu_data_master_requests_sysid_control_slave,
                                         d1_sysid_control_slave_end_xfer,
                                         sysid_control_slave_address,
                                         sysid_control_slave_readdata_from_sa,
                                         sysid_control_slave_reset_n
                                      )
;

  output           cpu_data_master_granted_sysid_control_slave;
  output           cpu_data_master_qualified_request_sysid_control_slave;
  output           cpu_data_master_read_data_valid_sysid_control_slave;
  output           cpu_data_master_requests_sysid_control_slave;
  output           d1_sysid_control_slave_end_xfer;
  output           sysid_control_slave_address;
  output  [ 31: 0] sysid_control_slave_readdata_from_sa;
  output           sysid_control_slave_reset_n;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input            reset_n;
  input   [ 31: 0] sysid_control_slave_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sysid_control_slave;
  wire             cpu_data_master_qualified_request_sysid_control_slave;
  wire             cpu_data_master_read_data_valid_sysid_control_slave;
  wire             cpu_data_master_requests_sysid_control_slave;
  wire             cpu_data_master_saved_grant_sysid_control_slave;
  reg              d1_reasons_to_wait;
  reg              d1_sysid_control_slave_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sysid_control_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_sysid_control_slave_from_cpu_data_master;
  wire             sysid_control_slave_address;
  wire             sysid_control_slave_allgrants;
  wire             sysid_control_slave_allow_new_arb_cycle;
  wire             sysid_control_slave_any_bursting_master_saved_grant;
  wire             sysid_control_slave_any_continuerequest;
  wire             sysid_control_slave_arb_counter_enable;
  reg     [  1: 0] sysid_control_slave_arb_share_counter;
  wire    [  1: 0] sysid_control_slave_arb_share_counter_next_value;
  wire    [  1: 0] sysid_control_slave_arb_share_set_values;
  wire             sysid_control_slave_beginbursttransfer_internal;
  wire             sysid_control_slave_begins_xfer;
  wire             sysid_control_slave_end_xfer;
  wire             sysid_control_slave_firsttransfer;
  wire             sysid_control_slave_grant_vector;
  wire             sysid_control_slave_in_a_read_cycle;
  wire             sysid_control_slave_in_a_write_cycle;
  wire             sysid_control_slave_master_qreq_vector;
  wire             sysid_control_slave_non_bursting_master_requests;
  wire    [ 31: 0] sysid_control_slave_readdata_from_sa;
  reg              sysid_control_slave_reg_firsttransfer;
  wire             sysid_control_slave_reset_n;
  reg              sysid_control_slave_slavearbiterlockenable;
  wire             sysid_control_slave_slavearbiterlockenable2;
  wire             sysid_control_slave_unreg_firsttransfer;
  wire             sysid_control_slave_waits_for_read;
  wire             sysid_control_slave_waits_for_write;
  wire             wait_for_sysid_control_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sysid_control_slave_end_xfer;
    end


  assign sysid_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sysid_control_slave));
  //assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata;

  assign cpu_data_master_requests_sysid_control_slave = (({cpu_data_master_address_to_slave[24 : 3] , 3'b0} == 25'h11090b8) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //sysid_control_slave_arb_share_counter set values, which is an e_mux
  assign sysid_control_slave_arb_share_set_values = 1;

  //sysid_control_slave_non_bursting_master_requests mux, which is an e_mux
  assign sysid_control_slave_non_bursting_master_requests = cpu_data_master_requests_sysid_control_slave;

  //sysid_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign sysid_control_slave_any_bursting_master_saved_grant = 0;

  //sysid_control_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign sysid_control_slave_arb_share_counter_next_value = sysid_control_slave_firsttransfer ? (sysid_control_slave_arb_share_set_values - 1) : |sysid_control_slave_arb_share_counter ? (sysid_control_slave_arb_share_counter - 1) : 0;

  //sysid_control_slave_allgrants all slave grants, which is an e_mux
  assign sysid_control_slave_allgrants = |sysid_control_slave_grant_vector;

  //sysid_control_slave_end_xfer assignment, which is an e_assign
  assign sysid_control_slave_end_xfer = ~(sysid_control_slave_waits_for_read | sysid_control_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_sysid_control_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sysid_control_slave = sysid_control_slave_end_xfer & (~sysid_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sysid_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign sysid_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_sysid_control_slave & sysid_control_slave_allgrants) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests);

  //sysid_control_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_arb_share_counter <= 0;
      else if (sysid_control_slave_arb_counter_enable)
          sysid_control_slave_arb_share_counter <= sysid_control_slave_arb_share_counter_next_value;
    end


  //sysid_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_slavearbiterlockenable <= 0;
      else if ((|sysid_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_sysid_control_slave) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests))
          sysid_control_slave_slavearbiterlockenable <= |sysid_control_slave_arb_share_counter_next_value;
    end


  //cpu/data_master sysid/control_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sysid_control_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sysid_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sysid_control_slave_slavearbiterlockenable2 = |sysid_control_slave_arb_share_counter_next_value;

  //cpu/data_master sysid/control_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sysid_control_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //sysid_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign sysid_control_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_sysid_control_slave = cpu_data_master_requests_sysid_control_slave & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_sysid_control_slave, which is an e_mux
  assign cpu_data_master_read_data_valid_sysid_control_slave = cpu_data_master_granted_sysid_control_slave & cpu_data_master_read & ~sysid_control_slave_waits_for_read;

  //master is always granted when requested
  assign cpu_data_master_granted_sysid_control_slave = cpu_data_master_qualified_request_sysid_control_slave;

  //cpu/data_master saved-grant sysid/control_slave, which is an e_assign
  assign cpu_data_master_saved_grant_sysid_control_slave = cpu_data_master_requests_sysid_control_slave;

  //allow new arb cycle for sysid/control_slave, which is an e_assign
  assign sysid_control_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign sysid_control_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign sysid_control_slave_master_qreq_vector = 1;

  //sysid_control_slave_reset_n assignment, which is an e_assign
  assign sysid_control_slave_reset_n = reset_n;

  //sysid_control_slave_firsttransfer first transaction, which is an e_assign
  assign sysid_control_slave_firsttransfer = sysid_control_slave_begins_xfer ? sysid_control_slave_unreg_firsttransfer : sysid_control_slave_reg_firsttransfer;

  //sysid_control_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign sysid_control_slave_unreg_firsttransfer = ~(sysid_control_slave_slavearbiterlockenable & sysid_control_slave_any_continuerequest);

  //sysid_control_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_reg_firsttransfer <= 1'b1;
      else if (sysid_control_slave_begins_xfer)
          sysid_control_slave_reg_firsttransfer <= sysid_control_slave_unreg_firsttransfer;
    end


  //sysid_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sysid_control_slave_beginbursttransfer_internal = sysid_control_slave_begins_xfer;

  assign shifted_address_to_sysid_control_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //sysid_control_slave_address mux, which is an e_mux
  assign sysid_control_slave_address = shifted_address_to_sysid_control_slave_from_cpu_data_master >> 2;

  //d1_sysid_control_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sysid_control_slave_end_xfer <= 1;
      else 
        d1_sysid_control_slave_end_xfer <= sysid_control_slave_end_xfer;
    end


  //sysid_control_slave_waits_for_read in a cycle, which is an e_mux
  assign sysid_control_slave_waits_for_read = sysid_control_slave_in_a_read_cycle & sysid_control_slave_begins_xfer;

  //sysid_control_slave_in_a_read_cycle assignment, which is an e_assign
  assign sysid_control_slave_in_a_read_cycle = cpu_data_master_granted_sysid_control_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sysid_control_slave_in_a_read_cycle;

  //sysid_control_slave_waits_for_write in a cycle, which is an e_mux
  assign sysid_control_slave_waits_for_write = sysid_control_slave_in_a_write_cycle & 0;

  //sysid_control_slave_in_a_write_cycle assignment, which is an e_assign
  assign sysid_control_slave_in_a_write_cycle = cpu_data_master_granted_sysid_control_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sysid_control_slave_in_a_write_cycle;

  assign wait_for_sysid_control_slave_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sysid/control_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module usr_timer_s1_arbitrator (
                                 // inputs:
                                  clk,
                                  cpu_data_master_address_to_slave,
                                  cpu_data_master_latency_counter,
                                  cpu_data_master_read,
                                  cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                  cpu_data_master_write,
                                  cpu_data_master_writedata,
                                  reset_n,
                                  usr_timer_s1_irq,
                                  usr_timer_s1_readdata,

                                 // outputs:
                                  cpu_data_master_granted_usr_timer_s1,
                                  cpu_data_master_qualified_request_usr_timer_s1,
                                  cpu_data_master_read_data_valid_usr_timer_s1,
                                  cpu_data_master_requests_usr_timer_s1,
                                  d1_usr_timer_s1_end_xfer,
                                  usr_timer_s1_address,
                                  usr_timer_s1_chipselect,
                                  usr_timer_s1_irq_from_sa,
                                  usr_timer_s1_readdata_from_sa,
                                  usr_timer_s1_reset_n,
                                  usr_timer_s1_write_n,
                                  usr_timer_s1_writedata
                               )
;

  output           cpu_data_master_granted_usr_timer_s1;
  output           cpu_data_master_qualified_request_usr_timer_s1;
  output           cpu_data_master_read_data_valid_usr_timer_s1;
  output           cpu_data_master_requests_usr_timer_s1;
  output           d1_usr_timer_s1_end_xfer;
  output  [  2: 0] usr_timer_s1_address;
  output           usr_timer_s1_chipselect;
  output           usr_timer_s1_irq_from_sa;
  output  [ 15: 0] usr_timer_s1_readdata_from_sa;
  output           usr_timer_s1_reset_n;
  output           usr_timer_s1_write_n;
  output  [ 15: 0] usr_timer_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  1: 0] cpu_data_master_latency_counter;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input            usr_timer_s1_irq;
  input   [ 15: 0] usr_timer_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_usr_timer_s1;
  wire             cpu_data_master_qualified_request_usr_timer_s1;
  wire             cpu_data_master_read_data_valid_usr_timer_s1;
  wire             cpu_data_master_requests_usr_timer_s1;
  wire             cpu_data_master_saved_grant_usr_timer_s1;
  reg              d1_reasons_to_wait;
  reg              d1_usr_timer_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_usr_timer_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_usr_timer_s1_from_cpu_data_master;
  wire    [  2: 0] usr_timer_s1_address;
  wire             usr_timer_s1_allgrants;
  wire             usr_timer_s1_allow_new_arb_cycle;
  wire             usr_timer_s1_any_bursting_master_saved_grant;
  wire             usr_timer_s1_any_continuerequest;
  wire             usr_timer_s1_arb_counter_enable;
  reg     [  1: 0] usr_timer_s1_arb_share_counter;
  wire    [  1: 0] usr_timer_s1_arb_share_counter_next_value;
  wire    [  1: 0] usr_timer_s1_arb_share_set_values;
  wire             usr_timer_s1_beginbursttransfer_internal;
  wire             usr_timer_s1_begins_xfer;
  wire             usr_timer_s1_chipselect;
  wire             usr_timer_s1_end_xfer;
  wire             usr_timer_s1_firsttransfer;
  wire             usr_timer_s1_grant_vector;
  wire             usr_timer_s1_in_a_read_cycle;
  wire             usr_timer_s1_in_a_write_cycle;
  wire             usr_timer_s1_irq_from_sa;
  wire             usr_timer_s1_master_qreq_vector;
  wire             usr_timer_s1_non_bursting_master_requests;
  wire    [ 15: 0] usr_timer_s1_readdata_from_sa;
  reg              usr_timer_s1_reg_firsttransfer;
  wire             usr_timer_s1_reset_n;
  reg              usr_timer_s1_slavearbiterlockenable;
  wire             usr_timer_s1_slavearbiterlockenable2;
  wire             usr_timer_s1_unreg_firsttransfer;
  wire             usr_timer_s1_waits_for_read;
  wire             usr_timer_s1_waits_for_write;
  wire             usr_timer_s1_write_n;
  wire    [ 15: 0] usr_timer_s1_writedata;
  wire             wait_for_usr_timer_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~usr_timer_s1_end_xfer;
    end


  assign usr_timer_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_usr_timer_s1));
  //assign usr_timer_s1_readdata_from_sa = usr_timer_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign usr_timer_s1_readdata_from_sa = usr_timer_s1_readdata;

  assign cpu_data_master_requests_usr_timer_s1 = ({cpu_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h1109020) & (cpu_data_master_read | cpu_data_master_write);
  //usr_timer_s1_arb_share_counter set values, which is an e_mux
  assign usr_timer_s1_arb_share_set_values = 1;

  //usr_timer_s1_non_bursting_master_requests mux, which is an e_mux
  assign usr_timer_s1_non_bursting_master_requests = cpu_data_master_requests_usr_timer_s1;

  //usr_timer_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign usr_timer_s1_any_bursting_master_saved_grant = 0;

  //usr_timer_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign usr_timer_s1_arb_share_counter_next_value = usr_timer_s1_firsttransfer ? (usr_timer_s1_arb_share_set_values - 1) : |usr_timer_s1_arb_share_counter ? (usr_timer_s1_arb_share_counter - 1) : 0;

  //usr_timer_s1_allgrants all slave grants, which is an e_mux
  assign usr_timer_s1_allgrants = |usr_timer_s1_grant_vector;

  //usr_timer_s1_end_xfer assignment, which is an e_assign
  assign usr_timer_s1_end_xfer = ~(usr_timer_s1_waits_for_read | usr_timer_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_usr_timer_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_usr_timer_s1 = usr_timer_s1_end_xfer & (~usr_timer_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //usr_timer_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign usr_timer_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_usr_timer_s1 & usr_timer_s1_allgrants) | (end_xfer_arb_share_counter_term_usr_timer_s1 & ~usr_timer_s1_non_bursting_master_requests);

  //usr_timer_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          usr_timer_s1_arb_share_counter <= 0;
      else if (usr_timer_s1_arb_counter_enable)
          usr_timer_s1_arb_share_counter <= usr_timer_s1_arb_share_counter_next_value;
    end


  //usr_timer_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          usr_timer_s1_slavearbiterlockenable <= 0;
      else if ((|usr_timer_s1_master_qreq_vector & end_xfer_arb_share_counter_term_usr_timer_s1) | (end_xfer_arb_share_counter_term_usr_timer_s1 & ~usr_timer_s1_non_bursting_master_requests))
          usr_timer_s1_slavearbiterlockenable <= |usr_timer_s1_arb_share_counter_next_value;
    end


  //cpu/data_master usr_timer/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = usr_timer_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //usr_timer_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign usr_timer_s1_slavearbiterlockenable2 = |usr_timer_s1_arb_share_counter_next_value;

  //cpu/data_master usr_timer/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = usr_timer_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //usr_timer_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign usr_timer_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_usr_timer_s1 = cpu_data_master_requests_usr_timer_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0) | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))));
  //local readdatavalid cpu_data_master_read_data_valid_usr_timer_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_usr_timer_s1 = cpu_data_master_granted_usr_timer_s1 & cpu_data_master_read & ~usr_timer_s1_waits_for_read;

  //usr_timer_s1_writedata mux, which is an e_mux
  assign usr_timer_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_usr_timer_s1 = cpu_data_master_qualified_request_usr_timer_s1;

  //cpu/data_master saved-grant usr_timer/s1, which is an e_assign
  assign cpu_data_master_saved_grant_usr_timer_s1 = cpu_data_master_requests_usr_timer_s1;

  //allow new arb cycle for usr_timer/s1, which is an e_assign
  assign usr_timer_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign usr_timer_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign usr_timer_s1_master_qreq_vector = 1;

  //usr_timer_s1_reset_n assignment, which is an e_assign
  assign usr_timer_s1_reset_n = reset_n;

  assign usr_timer_s1_chipselect = cpu_data_master_granted_usr_timer_s1;
  //usr_timer_s1_firsttransfer first transaction, which is an e_assign
  assign usr_timer_s1_firsttransfer = usr_timer_s1_begins_xfer ? usr_timer_s1_unreg_firsttransfer : usr_timer_s1_reg_firsttransfer;

  //usr_timer_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign usr_timer_s1_unreg_firsttransfer = ~(usr_timer_s1_slavearbiterlockenable & usr_timer_s1_any_continuerequest);

  //usr_timer_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          usr_timer_s1_reg_firsttransfer <= 1'b1;
      else if (usr_timer_s1_begins_xfer)
          usr_timer_s1_reg_firsttransfer <= usr_timer_s1_unreg_firsttransfer;
    end


  //usr_timer_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign usr_timer_s1_beginbursttransfer_internal = usr_timer_s1_begins_xfer;

  //~usr_timer_s1_write_n assignment, which is an e_mux
  assign usr_timer_s1_write_n = ~(cpu_data_master_granted_usr_timer_s1 & cpu_data_master_write);

  assign shifted_address_to_usr_timer_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //usr_timer_s1_address mux, which is an e_mux
  assign usr_timer_s1_address = shifted_address_to_usr_timer_s1_from_cpu_data_master >> 2;

  //d1_usr_timer_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_usr_timer_s1_end_xfer <= 1;
      else 
        d1_usr_timer_s1_end_xfer <= usr_timer_s1_end_xfer;
    end


  //usr_timer_s1_waits_for_read in a cycle, which is an e_mux
  assign usr_timer_s1_waits_for_read = usr_timer_s1_in_a_read_cycle & usr_timer_s1_begins_xfer;

  //usr_timer_s1_in_a_read_cycle assignment, which is an e_assign
  assign usr_timer_s1_in_a_read_cycle = cpu_data_master_granted_usr_timer_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = usr_timer_s1_in_a_read_cycle;

  //usr_timer_s1_waits_for_write in a cycle, which is an e_mux
  assign usr_timer_s1_waits_for_write = usr_timer_s1_in_a_write_cycle & 0;

  //usr_timer_s1_in_a_write_cycle assignment, which is an e_assign
  assign usr_timer_s1_in_a_write_cycle = cpu_data_master_granted_usr_timer_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = usr_timer_s1_in_a_write_cycle;

  assign wait_for_usr_timer_s1_counter = 0;
  //assign usr_timer_s1_irq_from_sa = usr_timer_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign usr_timer_s1_irq_from_sa = usr_timer_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //usr_timer/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nios_sd_card_reset_clk_sys_domain_synch_module (
                                                        // inputs:
                                                         clk,
                                                         data_in,
                                                         reset_n,

                                                        // outputs:
                                                         data_out
                                                      )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else 
        data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else 
        data_out <= data_in_d1;
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nios_sd_card_reset_clk_50M_domain_synch_module (
                                                        // inputs:
                                                         clk,
                                                         data_in,
                                                         reset_n,

                                                        // outputs:
                                                         data_out
                                                      )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else 
        data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else 
        data_out <= data_in_d1;
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nios_sd_card (
                      // 1) global signals:
                       clk_50M,
                       clk_sdram,
                       clk_sys,
                       reset_n,

                      // the_btn
                       in_port_to_the_btn,

                      // the_ledg
                       out_port_from_the_ledg,

                      // the_ledr
                       out_port_from_the_ledr,

                      // the_pll
                       areset_to_the_pll,
                       locked_from_the_pll,
                       phasedone_from_the_pll,

                      // the_sd_card
                       sd_clk_from_the_sd_card,
                       sd_cs_from_the_sd_card,
                       sd_di_from_the_sd_card,
                       sd_do_to_the_sd_card,

                      // the_sdram
                       zs_addr_from_the_sdram,
                       zs_ba_from_the_sdram,
                       zs_cas_n_from_the_sdram,
                       zs_cke_from_the_sdram,
                       zs_cs_n_from_the_sdram,
                       zs_dq_to_and_from_the_sdram,
                       zs_dqm_from_the_sdram,
                       zs_ras_n_from_the_sdram,
                       zs_we_n_from_the_sdram,

                      // the_sram
                       sram_addr_from_the_sram,
                       sram_ce_n_from_the_sram,
                       sram_dq_to_and_from_the_sram,
                       sram_lb_n_from_the_sram,
                       sram_oe_n_from_the_sram,
                       sram_ub_n_from_the_sram,
                       sram_we_n_from_the_sram,

                      // the_sseg
                       out_port_from_the_sseg,

                      // the_switch
                       in_port_to_the_switch
                    )
;

  output           clk_sdram;
  output           clk_sys;
  output           locked_from_the_pll;
  output  [  7: 0] out_port_from_the_ledg;
  output  [  9: 0] out_port_from_the_ledr;
  output  [ 31: 0] out_port_from_the_sseg;
  output           phasedone_from_the_pll;
  output           sd_clk_from_the_sd_card;
  output           sd_cs_from_the_sd_card;
  output           sd_di_from_the_sd_card;
  output  [ 17: 0] sram_addr_from_the_sram;
  output           sram_ce_n_from_the_sram;
  inout   [ 15: 0] sram_dq_to_and_from_the_sram;
  output           sram_lb_n_from_the_sram;
  output           sram_oe_n_from_the_sram;
  output           sram_ub_n_from_the_sram;
  output           sram_we_n_from_the_sram;
  output  [ 11: 0] zs_addr_from_the_sdram;
  output  [  1: 0] zs_ba_from_the_sdram;
  output           zs_cas_n_from_the_sdram;
  output           zs_cke_from_the_sdram;
  output           zs_cs_n_from_the_sdram;
  inout   [ 15: 0] zs_dq_to_and_from_the_sdram;
  output  [  1: 0] zs_dqm_from_the_sdram;
  output           zs_ras_n_from_the_sdram;
  output           zs_we_n_from_the_sdram;
  input            areset_to_the_pll;
  input            clk_50M;
  input   [  3: 0] in_port_to_the_btn;
  input   [  9: 0] in_port_to_the_switch;
  input            reset_n;
  input            sd_do_to_the_sd_card;

  wire    [  1: 0] btn_s1_address;
  wire             btn_s1_chipselect;
  wire             btn_s1_irq;
  wire             btn_s1_irq_from_sa;
  wire    [ 31: 0] btn_s1_readdata;
  wire    [ 31: 0] btn_s1_readdata_from_sa;
  wire             btn_s1_reset_n;
  wire             btn_s1_write_n;
  wire    [ 31: 0] btn_s1_writedata;
  wire             clk_50M_reset_n;
  wire             clk_sdram;
  wire             clk_sys;
  wire             clk_sys_reset_n;
  wire    [ 24: 0] cpu_data_master_address;
  wire    [ 24: 0] cpu_data_master_address_to_slave;
  wire    [  3: 0] cpu_data_master_byteenable;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1;
  wire    [  1: 0] cpu_data_master_byteenable_sram_cpu_ctrl;
  wire    [  1: 0] cpu_data_master_dbs_address;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire             cpu_data_master_debugaccess;
  wire             cpu_data_master_granted_btn_s1;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_granted_ledg_s1;
  wire             cpu_data_master_granted_ledr_s1;
  wire             cpu_data_master_granted_nios_sd_card_clock_0_in;
  wire             cpu_data_master_granted_onchip_mem_s1;
  wire             cpu_data_master_granted_sd_card_cpu_ctrl;
  wire             cpu_data_master_granted_sdram_s1;
  wire             cpu_data_master_granted_sram_cpu_ctrl;
  wire             cpu_data_master_granted_sseg_s1;
  wire             cpu_data_master_granted_switch_s1;
  wire             cpu_data_master_granted_sys_timer_s1;
  wire             cpu_data_master_granted_sysid_control_slave;
  wire             cpu_data_master_granted_usr_timer_s1;
  wire    [ 31: 0] cpu_data_master_irq;
  wire    [  1: 0] cpu_data_master_latency_counter;
  wire             cpu_data_master_qualified_request_btn_s1;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_ledg_s1;
  wire             cpu_data_master_qualified_request_ledr_s1;
  wire             cpu_data_master_qualified_request_nios_sd_card_clock_0_in;
  wire             cpu_data_master_qualified_request_onchip_mem_s1;
  wire             cpu_data_master_qualified_request_sd_card_cpu_ctrl;
  wire             cpu_data_master_qualified_request_sdram_s1;
  wire             cpu_data_master_qualified_request_sram_cpu_ctrl;
  wire             cpu_data_master_qualified_request_sseg_s1;
  wire             cpu_data_master_qualified_request_switch_s1;
  wire             cpu_data_master_qualified_request_sys_timer_s1;
  wire             cpu_data_master_qualified_request_sysid_control_slave;
  wire             cpu_data_master_qualified_request_usr_timer_s1;
  wire             cpu_data_master_read;
  wire             cpu_data_master_read_data_valid_btn_s1;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_ledg_s1;
  wire             cpu_data_master_read_data_valid_ledr_s1;
  wire             cpu_data_master_read_data_valid_nios_sd_card_clock_0_in;
  wire             cpu_data_master_read_data_valid_onchip_mem_s1;
  wire             cpu_data_master_read_data_valid_sd_card_cpu_ctrl;
  wire             cpu_data_master_read_data_valid_sdram_s1;
  wire             cpu_data_master_read_data_valid_sdram_s1_shift_register;
  wire             cpu_data_master_read_data_valid_sram_cpu_ctrl;
  wire             cpu_data_master_read_data_valid_sseg_s1;
  wire             cpu_data_master_read_data_valid_switch_s1;
  wire             cpu_data_master_read_data_valid_sys_timer_s1;
  wire             cpu_data_master_read_data_valid_sysid_control_slave;
  wire             cpu_data_master_read_data_valid_usr_timer_s1;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_readdatavalid;
  wire             cpu_data_master_requests_btn_s1;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_ledg_s1;
  wire             cpu_data_master_requests_ledr_s1;
  wire             cpu_data_master_requests_nios_sd_card_clock_0_in;
  wire             cpu_data_master_requests_onchip_mem_s1;
  wire             cpu_data_master_requests_sd_card_cpu_ctrl;
  wire             cpu_data_master_requests_sdram_s1;
  wire             cpu_data_master_requests_sram_cpu_ctrl;
  wire             cpu_data_master_requests_sseg_s1;
  wire             cpu_data_master_requests_switch_s1;
  wire             cpu_data_master_requests_sys_timer_s1;
  wire             cpu_data_master_requests_sysid_control_slave;
  wire             cpu_data_master_requests_usr_timer_s1;
  wire             cpu_data_master_waitrequest;
  wire             cpu_data_master_write;
  wire    [ 31: 0] cpu_data_master_writedata;
  wire    [ 24: 0] cpu_instruction_master_address;
  wire    [ 24: 0] cpu_instruction_master_address_to_slave;
  wire    [  1: 0] cpu_instruction_master_dbs_address;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_granted_onchip_mem_s1;
  wire             cpu_instruction_master_granted_sdram_s1;
  wire             cpu_instruction_master_granted_sram_cpu_ctrl;
  wire    [  1: 0] cpu_instruction_master_latency_counter;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_onchip_mem_s1;
  wire             cpu_instruction_master_qualified_request_sdram_s1;
  wire             cpu_instruction_master_qualified_request_sram_cpu_ctrl;
  wire             cpu_instruction_master_read;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_onchip_mem_s1;
  wire             cpu_instruction_master_read_data_valid_sdram_s1;
  wire             cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  wire             cpu_instruction_master_read_data_valid_sram_cpu_ctrl;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_onchip_mem_s1;
  wire             cpu_instruction_master_requests_sdram_s1;
  wire             cpu_instruction_master_requests_sram_cpu_ctrl;
  wire             cpu_instruction_master_waitrequest;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire             cpu_jtag_debug_module_debugaccess;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  wire             cpu_jtag_debug_module_reset_n;
  wire             cpu_jtag_debug_module_resetrequest;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  wire             d1_btn_s1_end_xfer;
  wire             d1_cpu_jtag_debug_module_end_xfer;
  wire             d1_jtag_uart_avalon_jtag_slave_end_xfer;
  wire             d1_ledg_s1_end_xfer;
  wire             d1_ledr_s1_end_xfer;
  wire             d1_nios_sd_card_clock_0_in_end_xfer;
  wire             d1_onchip_mem_s1_end_xfer;
  wire             d1_pll_pll_slave_end_xfer;
  wire             d1_sd_card_cpu_ctrl_end_xfer;
  wire             d1_sdram_s1_end_xfer;
  wire             d1_sram_cpu_ctrl_end_xfer;
  wire             d1_sseg_s1_end_xfer;
  wire             d1_switch_s1_end_xfer;
  wire             d1_sys_timer_s1_end_xfer;
  wire             d1_sysid_control_slave_end_xfer;
  wire             d1_usr_timer_s1_end_xfer;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_irq;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  wire             jtag_uart_avalon_jtag_slave_waitrequest;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [  1: 0] ledg_s1_address;
  wire             ledg_s1_chipselect;
  wire    [ 31: 0] ledg_s1_readdata;
  wire    [ 31: 0] ledg_s1_readdata_from_sa;
  wire             ledg_s1_reset_n;
  wire             ledg_s1_write_n;
  wire    [ 31: 0] ledg_s1_writedata;
  wire    [  1: 0] ledr_s1_address;
  wire             ledr_s1_chipselect;
  wire    [ 31: 0] ledr_s1_readdata;
  wire    [ 31: 0] ledr_s1_readdata_from_sa;
  wire             ledr_s1_reset_n;
  wire             ledr_s1_write_n;
  wire    [ 31: 0] ledr_s1_writedata;
  wire             locked_from_the_pll;
  wire    [  3: 0] nios_sd_card_clock_0_in_address;
  wire    [  3: 0] nios_sd_card_clock_0_in_byteenable;
  wire             nios_sd_card_clock_0_in_endofpacket;
  wire             nios_sd_card_clock_0_in_endofpacket_from_sa;
  wire    [  1: 0] nios_sd_card_clock_0_in_nativeaddress;
  wire             nios_sd_card_clock_0_in_read;
  wire    [ 31: 0] nios_sd_card_clock_0_in_readdata;
  wire    [ 31: 0] nios_sd_card_clock_0_in_readdata_from_sa;
  wire             nios_sd_card_clock_0_in_reset_n;
  wire             nios_sd_card_clock_0_in_waitrequest;
  wire             nios_sd_card_clock_0_in_waitrequest_from_sa;
  wire             nios_sd_card_clock_0_in_write;
  wire    [ 31: 0] nios_sd_card_clock_0_in_writedata;
  wire    [  3: 0] nios_sd_card_clock_0_out_address;
  wire    [  3: 0] nios_sd_card_clock_0_out_address_to_slave;
  wire    [  3: 0] nios_sd_card_clock_0_out_byteenable;
  wire             nios_sd_card_clock_0_out_endofpacket;
  wire             nios_sd_card_clock_0_out_granted_pll_pll_slave;
  wire    [  1: 0] nios_sd_card_clock_0_out_nativeaddress;
  wire             nios_sd_card_clock_0_out_qualified_request_pll_pll_slave;
  wire             nios_sd_card_clock_0_out_read;
  wire             nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave;
  wire    [ 31: 0] nios_sd_card_clock_0_out_readdata;
  wire             nios_sd_card_clock_0_out_requests_pll_pll_slave;
  wire             nios_sd_card_clock_0_out_reset_n;
  wire             nios_sd_card_clock_0_out_waitrequest;
  wire             nios_sd_card_clock_0_out_write;
  wire    [ 31: 0] nios_sd_card_clock_0_out_writedata;
  wire    [  8: 0] onchip_mem_s1_address;
  wire    [  3: 0] onchip_mem_s1_byteenable;
  wire             onchip_mem_s1_chipselect;
  wire             onchip_mem_s1_clken;
  wire    [ 31: 0] onchip_mem_s1_readdata;
  wire    [ 31: 0] onchip_mem_s1_readdata_from_sa;
  wire             onchip_mem_s1_reset;
  wire             onchip_mem_s1_write;
  wire    [ 31: 0] onchip_mem_s1_writedata;
  wire             out_clk_pll_c0;
  wire             out_clk_pll_c1;
  wire    [  7: 0] out_port_from_the_ledg;
  wire    [  9: 0] out_port_from_the_ledr;
  wire    [ 31: 0] out_port_from_the_sseg;
  wire             phasedone_from_the_pll;
  wire    [  1: 0] pll_pll_slave_address;
  wire             pll_pll_slave_read;
  wire    [ 31: 0] pll_pll_slave_readdata;
  wire    [ 31: 0] pll_pll_slave_readdata_from_sa;
  wire             pll_pll_slave_reset;
  wire             pll_pll_slave_write;
  wire    [ 31: 0] pll_pll_slave_writedata;
  wire             reset_n_sources;
  wire    [  1: 0] sd_card_cpu_ctrl_address;
  wire             sd_card_cpu_ctrl_chipselect;
  wire    [ 31: 0] sd_card_cpu_ctrl_readdata;
  wire    [ 31: 0] sd_card_cpu_ctrl_readdata_from_sa;
  wire             sd_card_cpu_ctrl_reset;
  wire             sd_card_cpu_ctrl_write;
  wire    [ 31: 0] sd_card_cpu_ctrl_writedata;
  wire             sd_clk_from_the_sd_card;
  wire             sd_cs_from_the_sd_card;
  wire             sd_di_from_the_sd_card;
  wire    [ 21: 0] sdram_s1_address;
  wire    [  1: 0] sdram_s1_byteenable_n;
  wire             sdram_s1_chipselect;
  wire             sdram_s1_read_n;
  wire    [ 15: 0] sdram_s1_readdata;
  wire    [ 15: 0] sdram_s1_readdata_from_sa;
  wire             sdram_s1_readdatavalid;
  wire             sdram_s1_reset_n;
  wire             sdram_s1_waitrequest;
  wire             sdram_s1_waitrequest_from_sa;
  wire             sdram_s1_write_n;
  wire    [ 15: 0] sdram_s1_writedata;
  wire    [ 17: 0] sram_addr_from_the_sram;
  wire             sram_ce_n_from_the_sram;
  wire    [ 17: 0] sram_cpu_ctrl_address;
  wire    [  1: 0] sram_cpu_ctrl_byteenable_n;
  wire             sram_cpu_ctrl_chipselect_n;
  wire             sram_cpu_ctrl_read_n;
  wire    [ 15: 0] sram_cpu_ctrl_readdata;
  wire    [ 15: 0] sram_cpu_ctrl_readdata_from_sa;
  wire             sram_cpu_ctrl_reset;
  wire             sram_cpu_ctrl_write_n;
  wire    [ 15: 0] sram_cpu_ctrl_writedata;
  wire    [ 15: 0] sram_dq_to_and_from_the_sram;
  wire             sram_lb_n_from_the_sram;
  wire             sram_oe_n_from_the_sram;
  wire             sram_ub_n_from_the_sram;
  wire             sram_we_n_from_the_sram;
  wire    [  1: 0] sseg_s1_address;
  wire             sseg_s1_chipselect;
  wire    [ 31: 0] sseg_s1_readdata;
  wire    [ 31: 0] sseg_s1_readdata_from_sa;
  wire             sseg_s1_reset_n;
  wire             sseg_s1_write_n;
  wire    [ 31: 0] sseg_s1_writedata;
  wire    [  1: 0] switch_s1_address;
  wire    [ 31: 0] switch_s1_readdata;
  wire    [ 31: 0] switch_s1_readdata_from_sa;
  wire             switch_s1_reset_n;
  wire    [  2: 0] sys_timer_s1_address;
  wire             sys_timer_s1_chipselect;
  wire             sys_timer_s1_irq;
  wire             sys_timer_s1_irq_from_sa;
  wire    [ 15: 0] sys_timer_s1_readdata;
  wire    [ 15: 0] sys_timer_s1_readdata_from_sa;
  wire             sys_timer_s1_reset_n;
  wire             sys_timer_s1_write_n;
  wire    [ 15: 0] sys_timer_s1_writedata;
  wire             sysid_control_slave_address;
  wire             sysid_control_slave_clock;
  wire    [ 31: 0] sysid_control_slave_readdata;
  wire    [ 31: 0] sysid_control_slave_readdata_from_sa;
  wire             sysid_control_slave_reset_n;
  wire    [  2: 0] usr_timer_s1_address;
  wire             usr_timer_s1_chipselect;
  wire             usr_timer_s1_irq;
  wire             usr_timer_s1_irq_from_sa;
  wire    [ 15: 0] usr_timer_s1_readdata;
  wire    [ 15: 0] usr_timer_s1_readdata_from_sa;
  wire             usr_timer_s1_reset_n;
  wire             usr_timer_s1_write_n;
  wire    [ 15: 0] usr_timer_s1_writedata;
  wire    [ 11: 0] zs_addr_from_the_sdram;
  wire    [  1: 0] zs_ba_from_the_sdram;
  wire             zs_cas_n_from_the_sdram;
  wire             zs_cke_from_the_sdram;
  wire             zs_cs_n_from_the_sdram;
  wire    [ 15: 0] zs_dq_to_and_from_the_sdram;
  wire    [  1: 0] zs_dqm_from_the_sdram;
  wire             zs_ras_n_from_the_sdram;
  wire             zs_we_n_from_the_sdram;
  btn_s1_arbitrator the_btn_s1
    (
      .btn_s1_address                                          (btn_s1_address),
      .btn_s1_chipselect                                       (btn_s1_chipselect),
      .btn_s1_irq                                              (btn_s1_irq),
      .btn_s1_irq_from_sa                                      (btn_s1_irq_from_sa),
      .btn_s1_readdata                                         (btn_s1_readdata),
      .btn_s1_readdata_from_sa                                 (btn_s1_readdata_from_sa),
      .btn_s1_reset_n                                          (btn_s1_reset_n),
      .btn_s1_write_n                                          (btn_s1_write_n),
      .btn_s1_writedata                                        (btn_s1_writedata),
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_btn_s1                          (cpu_data_master_granted_btn_s1),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_btn_s1                (cpu_data_master_qualified_request_btn_s1),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_btn_s1                  (cpu_data_master_read_data_valid_btn_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_btn_s1                         (cpu_data_master_requests_btn_s1),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .cpu_data_master_writedata                               (cpu_data_master_writedata),
      .d1_btn_s1_end_xfer                                      (d1_btn_s1_end_xfer),
      .reset_n                                                 (clk_sys_reset_n)
    );

  btn the_btn
    (
      .address    (btn_s1_address),
      .chipselect (btn_s1_chipselect),
      .clk        (clk_sys),
      .in_port    (in_port_to_the_btn),
      .irq        (btn_s1_irq),
      .readdata   (btn_s1_readdata),
      .reset_n    (btn_s1_reset_n),
      .write_n    (btn_s1_write_n),
      .writedata  (btn_s1_writedata)
    );

  cpu_jtag_debug_module_arbitrator the_cpu_jtag_debug_module
    (
      .clk                                                            (clk_sys),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_debugaccess                                    (cpu_data_master_debugaccess),
      .cpu_data_master_granted_cpu_jtag_debug_module                  (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_latency_counter                                (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module        (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module          (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register        (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_cpu_jtag_debug_module                 (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_data_master_writedata                                      (cpu_data_master_writedata),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_granted_cpu_jtag_debug_module           (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module   (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_requests_cpu_jtag_debug_module          (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_jtag_debug_module_address                                  (cpu_jtag_debug_module_address),
      .cpu_jtag_debug_module_begintransfer                            (cpu_jtag_debug_module_begintransfer),
      .cpu_jtag_debug_module_byteenable                               (cpu_jtag_debug_module_byteenable),
      .cpu_jtag_debug_module_chipselect                               (cpu_jtag_debug_module_chipselect),
      .cpu_jtag_debug_module_debugaccess                              (cpu_jtag_debug_module_debugaccess),
      .cpu_jtag_debug_module_readdata                                 (cpu_jtag_debug_module_readdata),
      .cpu_jtag_debug_module_readdata_from_sa                         (cpu_jtag_debug_module_readdata_from_sa),
      .cpu_jtag_debug_module_reset_n                                  (cpu_jtag_debug_module_reset_n),
      .cpu_jtag_debug_module_resetrequest                             (cpu_jtag_debug_module_resetrequest),
      .cpu_jtag_debug_module_resetrequest_from_sa                     (cpu_jtag_debug_module_resetrequest_from_sa),
      .cpu_jtag_debug_module_write                                    (cpu_jtag_debug_module_write),
      .cpu_jtag_debug_module_writedata                                (cpu_jtag_debug_module_writedata),
      .d1_cpu_jtag_debug_module_end_xfer                              (d1_cpu_jtag_debug_module_end_xfer),
      .reset_n                                                        (clk_sys_reset_n)
    );

  cpu_data_master_arbitrator the_cpu_data_master
    (
      .btn_s1_irq_from_sa                                            (btn_s1_irq_from_sa),
      .btn_s1_readdata_from_sa                                       (btn_s1_readdata_from_sa),
      .clk                                                           (clk_sys),
      .cpu_data_master_address                                       (cpu_data_master_address),
      .cpu_data_master_address_to_slave                              (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                    (cpu_data_master_byteenable),
      .cpu_data_master_byteenable_sdram_s1                           (cpu_data_master_byteenable_sdram_s1),
      .cpu_data_master_byteenable_sram_cpu_ctrl                      (cpu_data_master_byteenable_sram_cpu_ctrl),
      .cpu_data_master_dbs_address                                   (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                  (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_btn_s1                                (cpu_data_master_granted_btn_s1),
      .cpu_data_master_granted_cpu_jtag_debug_module                 (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave           (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_granted_ledg_s1                               (cpu_data_master_granted_ledg_s1),
      .cpu_data_master_granted_ledr_s1                               (cpu_data_master_granted_ledr_s1),
      .cpu_data_master_granted_nios_sd_card_clock_0_in               (cpu_data_master_granted_nios_sd_card_clock_0_in),
      .cpu_data_master_granted_onchip_mem_s1                         (cpu_data_master_granted_onchip_mem_s1),
      .cpu_data_master_granted_sd_card_cpu_ctrl                      (cpu_data_master_granted_sd_card_cpu_ctrl),
      .cpu_data_master_granted_sdram_s1                              (cpu_data_master_granted_sdram_s1),
      .cpu_data_master_granted_sram_cpu_ctrl                         (cpu_data_master_granted_sram_cpu_ctrl),
      .cpu_data_master_granted_sseg_s1                               (cpu_data_master_granted_sseg_s1),
      .cpu_data_master_granted_switch_s1                             (cpu_data_master_granted_switch_s1),
      .cpu_data_master_granted_sys_timer_s1                          (cpu_data_master_granted_sys_timer_s1),
      .cpu_data_master_granted_sysid_control_slave                   (cpu_data_master_granted_sysid_control_slave),
      .cpu_data_master_granted_usr_timer_s1                          (cpu_data_master_granted_usr_timer_s1),
      .cpu_data_master_irq                                           (cpu_data_master_irq),
      .cpu_data_master_latency_counter                               (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_btn_s1                      (cpu_data_master_qualified_request_btn_s1),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module       (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_qualified_request_ledg_s1                     (cpu_data_master_qualified_request_ledg_s1),
      .cpu_data_master_qualified_request_ledr_s1                     (cpu_data_master_qualified_request_ledr_s1),
      .cpu_data_master_qualified_request_nios_sd_card_clock_0_in     (cpu_data_master_qualified_request_nios_sd_card_clock_0_in),
      .cpu_data_master_qualified_request_onchip_mem_s1               (cpu_data_master_qualified_request_onchip_mem_s1),
      .cpu_data_master_qualified_request_sd_card_cpu_ctrl            (cpu_data_master_qualified_request_sd_card_cpu_ctrl),
      .cpu_data_master_qualified_request_sdram_s1                    (cpu_data_master_qualified_request_sdram_s1),
      .cpu_data_master_qualified_request_sram_cpu_ctrl               (cpu_data_master_qualified_request_sram_cpu_ctrl),
      .cpu_data_master_qualified_request_sseg_s1                     (cpu_data_master_qualified_request_sseg_s1),
      .cpu_data_master_qualified_request_switch_s1                   (cpu_data_master_qualified_request_switch_s1),
      .cpu_data_master_qualified_request_sys_timer_s1                (cpu_data_master_qualified_request_sys_timer_s1),
      .cpu_data_master_qualified_request_sysid_control_slave         (cpu_data_master_qualified_request_sysid_control_slave),
      .cpu_data_master_qualified_request_usr_timer_s1                (cpu_data_master_qualified_request_usr_timer_s1),
      .cpu_data_master_read                                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_btn_s1                        (cpu_data_master_read_data_valid_btn_s1),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module         (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave   (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read_data_valid_ledg_s1                       (cpu_data_master_read_data_valid_ledg_s1),
      .cpu_data_master_read_data_valid_ledr_s1                       (cpu_data_master_read_data_valid_ledr_s1),
      .cpu_data_master_read_data_valid_nios_sd_card_clock_0_in       (cpu_data_master_read_data_valid_nios_sd_card_clock_0_in),
      .cpu_data_master_read_data_valid_onchip_mem_s1                 (cpu_data_master_read_data_valid_onchip_mem_s1),
      .cpu_data_master_read_data_valid_sd_card_cpu_ctrl              (cpu_data_master_read_data_valid_sd_card_cpu_ctrl),
      .cpu_data_master_read_data_valid_sdram_s1                      (cpu_data_master_read_data_valid_sdram_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register       (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_sram_cpu_ctrl                 (cpu_data_master_read_data_valid_sram_cpu_ctrl),
      .cpu_data_master_read_data_valid_sseg_s1                       (cpu_data_master_read_data_valid_sseg_s1),
      .cpu_data_master_read_data_valid_switch_s1                     (cpu_data_master_read_data_valid_switch_s1),
      .cpu_data_master_read_data_valid_sys_timer_s1                  (cpu_data_master_read_data_valid_sys_timer_s1),
      .cpu_data_master_read_data_valid_sysid_control_slave           (cpu_data_master_read_data_valid_sysid_control_slave),
      .cpu_data_master_read_data_valid_usr_timer_s1                  (cpu_data_master_read_data_valid_usr_timer_s1),
      .cpu_data_master_readdata                                      (cpu_data_master_readdata),
      .cpu_data_master_readdatavalid                                 (cpu_data_master_readdatavalid),
      .cpu_data_master_requests_btn_s1                               (cpu_data_master_requests_btn_s1),
      .cpu_data_master_requests_cpu_jtag_debug_module                (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave          (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_requests_ledg_s1                              (cpu_data_master_requests_ledg_s1),
      .cpu_data_master_requests_ledr_s1                              (cpu_data_master_requests_ledr_s1),
      .cpu_data_master_requests_nios_sd_card_clock_0_in              (cpu_data_master_requests_nios_sd_card_clock_0_in),
      .cpu_data_master_requests_onchip_mem_s1                        (cpu_data_master_requests_onchip_mem_s1),
      .cpu_data_master_requests_sd_card_cpu_ctrl                     (cpu_data_master_requests_sd_card_cpu_ctrl),
      .cpu_data_master_requests_sdram_s1                             (cpu_data_master_requests_sdram_s1),
      .cpu_data_master_requests_sram_cpu_ctrl                        (cpu_data_master_requests_sram_cpu_ctrl),
      .cpu_data_master_requests_sseg_s1                              (cpu_data_master_requests_sseg_s1),
      .cpu_data_master_requests_switch_s1                            (cpu_data_master_requests_switch_s1),
      .cpu_data_master_requests_sys_timer_s1                         (cpu_data_master_requests_sys_timer_s1),
      .cpu_data_master_requests_sysid_control_slave                  (cpu_data_master_requests_sysid_control_slave),
      .cpu_data_master_requests_usr_timer_s1                         (cpu_data_master_requests_usr_timer_s1),
      .cpu_data_master_waitrequest                                   (cpu_data_master_waitrequest),
      .cpu_data_master_write                                         (cpu_data_master_write),
      .cpu_data_master_writedata                                     (cpu_data_master_writedata),
      .cpu_jtag_debug_module_readdata_from_sa                        (cpu_jtag_debug_module_readdata_from_sa),
      .d1_btn_s1_end_xfer                                            (d1_btn_s1_end_xfer),
      .d1_cpu_jtag_debug_module_end_xfer                             (d1_cpu_jtag_debug_module_end_xfer),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                       (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .d1_ledg_s1_end_xfer                                           (d1_ledg_s1_end_xfer),
      .d1_ledr_s1_end_xfer                                           (d1_ledr_s1_end_xfer),
      .d1_nios_sd_card_clock_0_in_end_xfer                           (d1_nios_sd_card_clock_0_in_end_xfer),
      .d1_onchip_mem_s1_end_xfer                                     (d1_onchip_mem_s1_end_xfer),
      .d1_sd_card_cpu_ctrl_end_xfer                                  (d1_sd_card_cpu_ctrl_end_xfer),
      .d1_sdram_s1_end_xfer                                          (d1_sdram_s1_end_xfer),
      .d1_sram_cpu_ctrl_end_xfer                                     (d1_sram_cpu_ctrl_end_xfer),
      .d1_sseg_s1_end_xfer                                           (d1_sseg_s1_end_xfer),
      .d1_switch_s1_end_xfer                                         (d1_switch_s1_end_xfer),
      .d1_sys_timer_s1_end_xfer                                      (d1_sys_timer_s1_end_xfer),
      .d1_sysid_control_slave_end_xfer                               (d1_sysid_control_slave_end_xfer),
      .d1_usr_timer_s1_end_xfer                                      (d1_usr_timer_s1_end_xfer),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                       (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                  (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa               (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .ledg_s1_readdata_from_sa                                      (ledg_s1_readdata_from_sa),
      .ledr_s1_readdata_from_sa                                      (ledr_s1_readdata_from_sa),
      .nios_sd_card_clock_0_in_readdata_from_sa                      (nios_sd_card_clock_0_in_readdata_from_sa),
      .nios_sd_card_clock_0_in_waitrequest_from_sa                   (nios_sd_card_clock_0_in_waitrequest_from_sa),
      .onchip_mem_s1_readdata_from_sa                                (onchip_mem_s1_readdata_from_sa),
      .reset_n                                                       (clk_sys_reset_n),
      .sd_card_cpu_ctrl_readdata_from_sa                             (sd_card_cpu_ctrl_readdata_from_sa),
      .sdram_s1_readdata_from_sa                                     (sdram_s1_readdata_from_sa),
      .sdram_s1_waitrequest_from_sa                                  (sdram_s1_waitrequest_from_sa),
      .sram_cpu_ctrl_readdata_from_sa                                (sram_cpu_ctrl_readdata_from_sa),
      .sseg_s1_readdata_from_sa                                      (sseg_s1_readdata_from_sa),
      .switch_s1_readdata_from_sa                                    (switch_s1_readdata_from_sa),
      .sys_timer_s1_irq_from_sa                                      (sys_timer_s1_irq_from_sa),
      .sys_timer_s1_readdata_from_sa                                 (sys_timer_s1_readdata_from_sa),
      .sysid_control_slave_readdata_from_sa                          (sysid_control_slave_readdata_from_sa),
      .usr_timer_s1_irq_from_sa                                      (usr_timer_s1_irq_from_sa),
      .usr_timer_s1_readdata_from_sa                                 (usr_timer_s1_readdata_from_sa)
    );

  cpu_instruction_master_arbitrator the_cpu_instruction_master
    (
      .clk                                                            (clk_sys),
      .cpu_instruction_master_address                                 (cpu_instruction_master_address),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                             (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_cpu_jtag_debug_module           (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_granted_onchip_mem_s1                   (cpu_instruction_master_granted_onchip_mem_s1),
      .cpu_instruction_master_granted_sdram_s1                        (cpu_instruction_master_granted_sdram_s1),
      .cpu_instruction_master_granted_sram_cpu_ctrl                   (cpu_instruction_master_granted_sram_cpu_ctrl),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_qualified_request_onchip_mem_s1         (cpu_instruction_master_qualified_request_onchip_mem_s1),
      .cpu_instruction_master_qualified_request_sdram_s1              (cpu_instruction_master_qualified_request_sdram_s1),
      .cpu_instruction_master_qualified_request_sram_cpu_ctrl         (cpu_instruction_master_qualified_request_sram_cpu_ctrl),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module   (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_read_data_valid_onchip_mem_s1           (cpu_instruction_master_read_data_valid_onchip_mem_s1),
      .cpu_instruction_master_read_data_valid_sdram_s1                (cpu_instruction_master_read_data_valid_sdram_s1),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_read_data_valid_sram_cpu_ctrl           (cpu_instruction_master_read_data_valid_sram_cpu_ctrl),
      .cpu_instruction_master_readdata                                (cpu_instruction_master_readdata),
      .cpu_instruction_master_readdatavalid                           (cpu_instruction_master_readdatavalid),
      .cpu_instruction_master_requests_cpu_jtag_debug_module          (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_instruction_master_requests_onchip_mem_s1                  (cpu_instruction_master_requests_onchip_mem_s1),
      .cpu_instruction_master_requests_sdram_s1                       (cpu_instruction_master_requests_sdram_s1),
      .cpu_instruction_master_requests_sram_cpu_ctrl                  (cpu_instruction_master_requests_sram_cpu_ctrl),
      .cpu_instruction_master_waitrequest                             (cpu_instruction_master_waitrequest),
      .cpu_jtag_debug_module_readdata_from_sa                         (cpu_jtag_debug_module_readdata_from_sa),
      .d1_cpu_jtag_debug_module_end_xfer                              (d1_cpu_jtag_debug_module_end_xfer),
      .d1_onchip_mem_s1_end_xfer                                      (d1_onchip_mem_s1_end_xfer),
      .d1_sdram_s1_end_xfer                                           (d1_sdram_s1_end_xfer),
      .d1_sram_cpu_ctrl_end_xfer                                      (d1_sram_cpu_ctrl_end_xfer),
      .onchip_mem_s1_readdata_from_sa                                 (onchip_mem_s1_readdata_from_sa),
      .reset_n                                                        (clk_sys_reset_n),
      .sdram_s1_readdata_from_sa                                      (sdram_s1_readdata_from_sa),
      .sdram_s1_waitrequest_from_sa                                   (sdram_s1_waitrequest_from_sa),
      .sram_cpu_ctrl_readdata_from_sa                                 (sram_cpu_ctrl_readdata_from_sa)
    );

  cpu the_cpu
    (
      .clk                                   (clk_sys),
      .d_address                             (cpu_data_master_address),
      .d_byteenable                          (cpu_data_master_byteenable),
      .d_irq                                 (cpu_data_master_irq),
      .d_read                                (cpu_data_master_read),
      .d_readdata                            (cpu_data_master_readdata),
      .d_readdatavalid                       (cpu_data_master_readdatavalid),
      .d_waitrequest                         (cpu_data_master_waitrequest),
      .d_write                               (cpu_data_master_write),
      .d_writedata                           (cpu_data_master_writedata),
      .i_address                             (cpu_instruction_master_address),
      .i_read                                (cpu_instruction_master_read),
      .i_readdata                            (cpu_instruction_master_readdata),
      .i_readdatavalid                       (cpu_instruction_master_readdatavalid),
      .i_waitrequest                         (cpu_instruction_master_waitrequest),
      .jtag_debug_module_address             (cpu_jtag_debug_module_address),
      .jtag_debug_module_begintransfer       (cpu_jtag_debug_module_begintransfer),
      .jtag_debug_module_byteenable          (cpu_jtag_debug_module_byteenable),
      .jtag_debug_module_debugaccess         (cpu_jtag_debug_module_debugaccess),
      .jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess),
      .jtag_debug_module_readdata            (cpu_jtag_debug_module_readdata),
      .jtag_debug_module_resetrequest        (cpu_jtag_debug_module_resetrequest),
      .jtag_debug_module_select              (cpu_jtag_debug_module_chipselect),
      .jtag_debug_module_write               (cpu_jtag_debug_module_write),
      .jtag_debug_module_writedata           (cpu_jtag_debug_module_writedata),
      .reset_n                               (cpu_jtag_debug_module_reset_n)
    );

  jtag_uart_avalon_jtag_slave_arbitrator the_jtag_uart_avalon_jtag_slave
    (
      .clk                                                           (clk_sys),
      .cpu_data_master_address_to_slave                              (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave           (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_latency_counter                               (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read                                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave   (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register       (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave          (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_write                                         (cpu_data_master_write),
      .cpu_data_master_writedata                                     (cpu_data_master_writedata),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                       (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .jtag_uart_avalon_jtag_slave_address                           (jtag_uart_avalon_jtag_slave_address),
      .jtag_uart_avalon_jtag_slave_chipselect                        (jtag_uart_avalon_jtag_slave_chipselect),
      .jtag_uart_avalon_jtag_slave_dataavailable                     (jtag_uart_avalon_jtag_slave_dataavailable),
      .jtag_uart_avalon_jtag_slave_dataavailable_from_sa             (jtag_uart_avalon_jtag_slave_dataavailable_from_sa),
      .jtag_uart_avalon_jtag_slave_irq                               (jtag_uart_avalon_jtag_slave_irq),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                       (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_read_n                            (jtag_uart_avalon_jtag_slave_read_n),
      .jtag_uart_avalon_jtag_slave_readdata                          (jtag_uart_avalon_jtag_slave_readdata),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                  (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_readyfordata                      (jtag_uart_avalon_jtag_slave_readyfordata),
      .jtag_uart_avalon_jtag_slave_readyfordata_from_sa              (jtag_uart_avalon_jtag_slave_readyfordata_from_sa),
      .jtag_uart_avalon_jtag_slave_reset_n                           (jtag_uart_avalon_jtag_slave_reset_n),
      .jtag_uart_avalon_jtag_slave_waitrequest                       (jtag_uart_avalon_jtag_slave_waitrequest),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa               (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_avalon_jtag_slave_write_n                           (jtag_uart_avalon_jtag_slave_write_n),
      .jtag_uart_avalon_jtag_slave_writedata                         (jtag_uart_avalon_jtag_slave_writedata),
      .reset_n                                                       (clk_sys_reset_n)
    );

  jtag_uart the_jtag_uart
    (
      .av_address     (jtag_uart_avalon_jtag_slave_address),
      .av_chipselect  (jtag_uart_avalon_jtag_slave_chipselect),
      .av_irq         (jtag_uart_avalon_jtag_slave_irq),
      .av_read_n      (jtag_uart_avalon_jtag_slave_read_n),
      .av_readdata    (jtag_uart_avalon_jtag_slave_readdata),
      .av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
      .av_write_n     (jtag_uart_avalon_jtag_slave_write_n),
      .av_writedata   (jtag_uart_avalon_jtag_slave_writedata),
      .clk            (clk_sys),
      .dataavailable  (jtag_uart_avalon_jtag_slave_dataavailable),
      .readyfordata   (jtag_uart_avalon_jtag_slave_readyfordata),
      .rst_n          (jtag_uart_avalon_jtag_slave_reset_n)
    );

  ledg_s1_arbitrator the_ledg_s1
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_ledg_s1                         (cpu_data_master_granted_ledg_s1),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_ledg_s1               (cpu_data_master_qualified_request_ledg_s1),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_ledg_s1                 (cpu_data_master_read_data_valid_ledg_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_ledg_s1                        (cpu_data_master_requests_ledg_s1),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .cpu_data_master_writedata                               (cpu_data_master_writedata),
      .d1_ledg_s1_end_xfer                                     (d1_ledg_s1_end_xfer),
      .ledg_s1_address                                         (ledg_s1_address),
      .ledg_s1_chipselect                                      (ledg_s1_chipselect),
      .ledg_s1_readdata                                        (ledg_s1_readdata),
      .ledg_s1_readdata_from_sa                                (ledg_s1_readdata_from_sa),
      .ledg_s1_reset_n                                         (ledg_s1_reset_n),
      .ledg_s1_write_n                                         (ledg_s1_write_n),
      .ledg_s1_writedata                                       (ledg_s1_writedata),
      .reset_n                                                 (clk_sys_reset_n)
    );

  ledg the_ledg
    (
      .address    (ledg_s1_address),
      .chipselect (ledg_s1_chipselect),
      .clk        (clk_sys),
      .out_port   (out_port_from_the_ledg),
      .readdata   (ledg_s1_readdata),
      .reset_n    (ledg_s1_reset_n),
      .write_n    (ledg_s1_write_n),
      .writedata  (ledg_s1_writedata)
    );

  ledr_s1_arbitrator the_ledr_s1
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_ledr_s1                         (cpu_data_master_granted_ledr_s1),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_ledr_s1               (cpu_data_master_qualified_request_ledr_s1),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_ledr_s1                 (cpu_data_master_read_data_valid_ledr_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_ledr_s1                        (cpu_data_master_requests_ledr_s1),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .cpu_data_master_writedata                               (cpu_data_master_writedata),
      .d1_ledr_s1_end_xfer                                     (d1_ledr_s1_end_xfer),
      .ledr_s1_address                                         (ledr_s1_address),
      .ledr_s1_chipselect                                      (ledr_s1_chipselect),
      .ledr_s1_readdata                                        (ledr_s1_readdata),
      .ledr_s1_readdata_from_sa                                (ledr_s1_readdata_from_sa),
      .ledr_s1_reset_n                                         (ledr_s1_reset_n),
      .ledr_s1_write_n                                         (ledr_s1_write_n),
      .ledr_s1_writedata                                       (ledr_s1_writedata),
      .reset_n                                                 (clk_sys_reset_n)
    );

  ledr the_ledr
    (
      .address    (ledr_s1_address),
      .chipselect (ledr_s1_chipselect),
      .clk        (clk_sys),
      .out_port   (out_port_from_the_ledr),
      .readdata   (ledr_s1_readdata),
      .reset_n    (ledr_s1_reset_n),
      .write_n    (ledr_s1_write_n),
      .writedata  (ledr_s1_writedata)
    );

  nios_sd_card_clock_0_in_arbitrator the_nios_sd_card_clock_0_in
    (
      .clk                                                       (clk_sys),
      .cpu_data_master_address_to_slave                          (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                (cpu_data_master_byteenable),
      .cpu_data_master_granted_nios_sd_card_clock_0_in           (cpu_data_master_granted_nios_sd_card_clock_0_in),
      .cpu_data_master_latency_counter                           (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_nios_sd_card_clock_0_in (cpu_data_master_qualified_request_nios_sd_card_clock_0_in),
      .cpu_data_master_read                                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_nios_sd_card_clock_0_in   (cpu_data_master_read_data_valid_nios_sd_card_clock_0_in),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register   (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_nios_sd_card_clock_0_in          (cpu_data_master_requests_nios_sd_card_clock_0_in),
      .cpu_data_master_write                                     (cpu_data_master_write),
      .cpu_data_master_writedata                                 (cpu_data_master_writedata),
      .d1_nios_sd_card_clock_0_in_end_xfer                       (d1_nios_sd_card_clock_0_in_end_xfer),
      .nios_sd_card_clock_0_in_address                           (nios_sd_card_clock_0_in_address),
      .nios_sd_card_clock_0_in_byteenable                        (nios_sd_card_clock_0_in_byteenable),
      .nios_sd_card_clock_0_in_endofpacket                       (nios_sd_card_clock_0_in_endofpacket),
      .nios_sd_card_clock_0_in_endofpacket_from_sa               (nios_sd_card_clock_0_in_endofpacket_from_sa),
      .nios_sd_card_clock_0_in_nativeaddress                     (nios_sd_card_clock_0_in_nativeaddress),
      .nios_sd_card_clock_0_in_read                              (nios_sd_card_clock_0_in_read),
      .nios_sd_card_clock_0_in_readdata                          (nios_sd_card_clock_0_in_readdata),
      .nios_sd_card_clock_0_in_readdata_from_sa                  (nios_sd_card_clock_0_in_readdata_from_sa),
      .nios_sd_card_clock_0_in_reset_n                           (nios_sd_card_clock_0_in_reset_n),
      .nios_sd_card_clock_0_in_waitrequest                       (nios_sd_card_clock_0_in_waitrequest),
      .nios_sd_card_clock_0_in_waitrequest_from_sa               (nios_sd_card_clock_0_in_waitrequest_from_sa),
      .nios_sd_card_clock_0_in_write                             (nios_sd_card_clock_0_in_write),
      .nios_sd_card_clock_0_in_writedata                         (nios_sd_card_clock_0_in_writedata),
      .reset_n                                                   (clk_sys_reset_n)
    );

  nios_sd_card_clock_0_out_arbitrator the_nios_sd_card_clock_0_out
    (
      .clk                                                      (clk_50M),
      .d1_pll_pll_slave_end_xfer                                (d1_pll_pll_slave_end_xfer),
      .nios_sd_card_clock_0_out_address                         (nios_sd_card_clock_0_out_address),
      .nios_sd_card_clock_0_out_address_to_slave                (nios_sd_card_clock_0_out_address_to_slave),
      .nios_sd_card_clock_0_out_byteenable                      (nios_sd_card_clock_0_out_byteenable),
      .nios_sd_card_clock_0_out_granted_pll_pll_slave           (nios_sd_card_clock_0_out_granted_pll_pll_slave),
      .nios_sd_card_clock_0_out_qualified_request_pll_pll_slave (nios_sd_card_clock_0_out_qualified_request_pll_pll_slave),
      .nios_sd_card_clock_0_out_read                            (nios_sd_card_clock_0_out_read),
      .nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave   (nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave),
      .nios_sd_card_clock_0_out_readdata                        (nios_sd_card_clock_0_out_readdata),
      .nios_sd_card_clock_0_out_requests_pll_pll_slave          (nios_sd_card_clock_0_out_requests_pll_pll_slave),
      .nios_sd_card_clock_0_out_reset_n                         (nios_sd_card_clock_0_out_reset_n),
      .nios_sd_card_clock_0_out_waitrequest                     (nios_sd_card_clock_0_out_waitrequest),
      .nios_sd_card_clock_0_out_write                           (nios_sd_card_clock_0_out_write),
      .nios_sd_card_clock_0_out_writedata                       (nios_sd_card_clock_0_out_writedata),
      .pll_pll_slave_readdata_from_sa                           (pll_pll_slave_readdata_from_sa),
      .reset_n                                                  (clk_50M_reset_n)
    );

  nios_sd_card_clock_0 the_nios_sd_card_clock_0
    (
      .master_address       (nios_sd_card_clock_0_out_address),
      .master_byteenable    (nios_sd_card_clock_0_out_byteenable),
      .master_clk           (clk_50M),
      .master_endofpacket   (nios_sd_card_clock_0_out_endofpacket),
      .master_nativeaddress (nios_sd_card_clock_0_out_nativeaddress),
      .master_read          (nios_sd_card_clock_0_out_read),
      .master_readdata      (nios_sd_card_clock_0_out_readdata),
      .master_reset_n       (nios_sd_card_clock_0_out_reset_n),
      .master_waitrequest   (nios_sd_card_clock_0_out_waitrequest),
      .master_write         (nios_sd_card_clock_0_out_write),
      .master_writedata     (nios_sd_card_clock_0_out_writedata),
      .slave_address        (nios_sd_card_clock_0_in_address),
      .slave_byteenable     (nios_sd_card_clock_0_in_byteenable),
      .slave_clk            (clk_sys),
      .slave_endofpacket    (nios_sd_card_clock_0_in_endofpacket),
      .slave_nativeaddress  (nios_sd_card_clock_0_in_nativeaddress),
      .slave_read           (nios_sd_card_clock_0_in_read),
      .slave_readdata       (nios_sd_card_clock_0_in_readdata),
      .slave_reset_n        (nios_sd_card_clock_0_in_reset_n),
      .slave_waitrequest    (nios_sd_card_clock_0_in_waitrequest),
      .slave_write          (nios_sd_card_clock_0_in_write),
      .slave_writedata      (nios_sd_card_clock_0_in_writedata)
    );

  onchip_mem_s1_arbitrator the_onchip_mem_s1
    (
      .clk                                                            (clk_sys),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_granted_onchip_mem_s1                          (cpu_data_master_granted_onchip_mem_s1),
      .cpu_data_master_latency_counter                                (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_onchip_mem_s1                (cpu_data_master_qualified_request_onchip_mem_s1),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_onchip_mem_s1                  (cpu_data_master_read_data_valid_onchip_mem_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register        (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_onchip_mem_s1                         (cpu_data_master_requests_onchip_mem_s1),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_data_master_writedata                                      (cpu_data_master_writedata),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_granted_onchip_mem_s1                   (cpu_instruction_master_granted_onchip_mem_s1),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_onchip_mem_s1         (cpu_instruction_master_qualified_request_onchip_mem_s1),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_onchip_mem_s1           (cpu_instruction_master_read_data_valid_onchip_mem_s1),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_requests_onchip_mem_s1                  (cpu_instruction_master_requests_onchip_mem_s1),
      .d1_onchip_mem_s1_end_xfer                                      (d1_onchip_mem_s1_end_xfer),
      .onchip_mem_s1_address                                          (onchip_mem_s1_address),
      .onchip_mem_s1_byteenable                                       (onchip_mem_s1_byteenable),
      .onchip_mem_s1_chipselect                                       (onchip_mem_s1_chipselect),
      .onchip_mem_s1_clken                                            (onchip_mem_s1_clken),
      .onchip_mem_s1_readdata                                         (onchip_mem_s1_readdata),
      .onchip_mem_s1_readdata_from_sa                                 (onchip_mem_s1_readdata_from_sa),
      .onchip_mem_s1_reset                                            (onchip_mem_s1_reset),
      .onchip_mem_s1_write                                            (onchip_mem_s1_write),
      .onchip_mem_s1_writedata                                        (onchip_mem_s1_writedata),
      .reset_n                                                        (clk_sys_reset_n)
    );

  onchip_mem the_onchip_mem
    (
      .address    (onchip_mem_s1_address),
      .byteenable (onchip_mem_s1_byteenable),
      .chipselect (onchip_mem_s1_chipselect),
      .clk        (clk_sys),
      .clken      (onchip_mem_s1_clken),
      .readdata   (onchip_mem_s1_readdata),
      .reset      (onchip_mem_s1_reset),
      .write      (onchip_mem_s1_write),
      .writedata  (onchip_mem_s1_writedata)
    );

  pll_pll_slave_arbitrator the_pll_pll_slave
    (
      .clk                                                      (clk_50M),
      .d1_pll_pll_slave_end_xfer                                (d1_pll_pll_slave_end_xfer),
      .nios_sd_card_clock_0_out_address_to_slave                (nios_sd_card_clock_0_out_address_to_slave),
      .nios_sd_card_clock_0_out_granted_pll_pll_slave           (nios_sd_card_clock_0_out_granted_pll_pll_slave),
      .nios_sd_card_clock_0_out_qualified_request_pll_pll_slave (nios_sd_card_clock_0_out_qualified_request_pll_pll_slave),
      .nios_sd_card_clock_0_out_read                            (nios_sd_card_clock_0_out_read),
      .nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave   (nios_sd_card_clock_0_out_read_data_valid_pll_pll_slave),
      .nios_sd_card_clock_0_out_requests_pll_pll_slave          (nios_sd_card_clock_0_out_requests_pll_pll_slave),
      .nios_sd_card_clock_0_out_write                           (nios_sd_card_clock_0_out_write),
      .nios_sd_card_clock_0_out_writedata                       (nios_sd_card_clock_0_out_writedata),
      .pll_pll_slave_address                                    (pll_pll_slave_address),
      .pll_pll_slave_read                                       (pll_pll_slave_read),
      .pll_pll_slave_readdata                                   (pll_pll_slave_readdata),
      .pll_pll_slave_readdata_from_sa                           (pll_pll_slave_readdata_from_sa),
      .pll_pll_slave_reset                                      (pll_pll_slave_reset),
      .pll_pll_slave_write                                      (pll_pll_slave_write),
      .pll_pll_slave_writedata                                  (pll_pll_slave_writedata),
      .reset_n                                                  (clk_50M_reset_n)
    );

  //clk_sys out_clk assignment, which is an e_assign
  assign clk_sys = out_clk_pll_c0;

  //clk_sdram out_clk assignment, which is an e_assign
  assign clk_sdram = out_clk_pll_c1;

  pll the_pll
    (
      .address   (pll_pll_slave_address),
      .areset    (areset_to_the_pll),
      .c0        (out_clk_pll_c0),
      .c1        (out_clk_pll_c1),
      .clk       (clk_50M),
      .locked    (locked_from_the_pll),
      .phasedone (phasedone_from_the_pll),
      .read      (pll_pll_slave_read),
      .readdata  (pll_pll_slave_readdata),
      .reset     (pll_pll_slave_reset),
      .write     (pll_pll_slave_write),
      .writedata (pll_pll_slave_writedata)
    );

  sd_card_cpu_ctrl_arbitrator the_sd_card_cpu_ctrl
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_sd_card_cpu_ctrl                (cpu_data_master_granted_sd_card_cpu_ctrl),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_sd_card_cpu_ctrl      (cpu_data_master_qualified_request_sd_card_cpu_ctrl),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sd_card_cpu_ctrl        (cpu_data_master_read_data_valid_sd_card_cpu_ctrl),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_sd_card_cpu_ctrl               (cpu_data_master_requests_sd_card_cpu_ctrl),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .cpu_data_master_writedata                               (cpu_data_master_writedata),
      .d1_sd_card_cpu_ctrl_end_xfer                            (d1_sd_card_cpu_ctrl_end_xfer),
      .reset_n                                                 (clk_sys_reset_n),
      .sd_card_cpu_ctrl_address                                (sd_card_cpu_ctrl_address),
      .sd_card_cpu_ctrl_chipselect                             (sd_card_cpu_ctrl_chipselect),
      .sd_card_cpu_ctrl_readdata                               (sd_card_cpu_ctrl_readdata),
      .sd_card_cpu_ctrl_readdata_from_sa                       (sd_card_cpu_ctrl_readdata_from_sa),
      .sd_card_cpu_ctrl_reset                                  (sd_card_cpu_ctrl_reset),
      .sd_card_cpu_ctrl_write                                  (sd_card_cpu_ctrl_write),
      .sd_card_cpu_ctrl_writedata                              (sd_card_cpu_ctrl_writedata)
    );

  sd_card the_sd_card
    (
      .clk           (clk_sys),
      .reset         (sd_card_cpu_ctrl_reset),
      .sd_address    (sd_card_cpu_ctrl_address),
      .sd_chipselect (sd_card_cpu_ctrl_chipselect),
      .sd_clk        (sd_clk_from_the_sd_card),
      .sd_cs         (sd_cs_from_the_sd_card),
      .sd_di         (sd_di_from_the_sd_card),
      .sd_do         (sd_do_to_the_sd_card),
      .sd_readdata   (sd_card_cpu_ctrl_readdata),
      .sd_write      (sd_card_cpu_ctrl_write),
      .sd_writedata  (sd_card_cpu_ctrl_writedata)
    );

  sdram_s1_arbitrator the_sdram_s1
    (
      .clk                                                            (clk_sys),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_byteenable_sdram_s1                            (cpu_data_master_byteenable_sdram_s1),
      .cpu_data_master_dbs_address                                    (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                   (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_sdram_s1                               (cpu_data_master_granted_sdram_s1),
      .cpu_data_master_latency_counter                                (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_sdram_s1                     (cpu_data_master_qualified_request_sdram_s1),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1                       (cpu_data_master_read_data_valid_sdram_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register        (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_sdram_s1                              (cpu_data_master_requests_sdram_s1),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                             (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_sdram_s1                        (cpu_instruction_master_granted_sdram_s1),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_sdram_s1              (cpu_instruction_master_qualified_request_sdram_s1),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_sdram_s1                (cpu_instruction_master_read_data_valid_sdram_s1),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_requests_sdram_s1                       (cpu_instruction_master_requests_sdram_s1),
      .d1_sdram_s1_end_xfer                                           (d1_sdram_s1_end_xfer),
      .reset_n                                                        (clk_sys_reset_n),
      .sdram_s1_address                                               (sdram_s1_address),
      .sdram_s1_byteenable_n                                          (sdram_s1_byteenable_n),
      .sdram_s1_chipselect                                            (sdram_s1_chipselect),
      .sdram_s1_read_n                                                (sdram_s1_read_n),
      .sdram_s1_readdata                                              (sdram_s1_readdata),
      .sdram_s1_readdata_from_sa                                      (sdram_s1_readdata_from_sa),
      .sdram_s1_readdatavalid                                         (sdram_s1_readdatavalid),
      .sdram_s1_reset_n                                               (sdram_s1_reset_n),
      .sdram_s1_waitrequest                                           (sdram_s1_waitrequest),
      .sdram_s1_waitrequest_from_sa                                   (sdram_s1_waitrequest_from_sa),
      .sdram_s1_write_n                                               (sdram_s1_write_n),
      .sdram_s1_writedata                                             (sdram_s1_writedata)
    );

  sdram the_sdram
    (
      .az_addr        (sdram_s1_address),
      .az_be_n        (sdram_s1_byteenable_n),
      .az_cs          (sdram_s1_chipselect),
      .az_data        (sdram_s1_writedata),
      .az_rd_n        (sdram_s1_read_n),
      .az_wr_n        (sdram_s1_write_n),
      .clk            (clk_sys),
      .reset_n        (sdram_s1_reset_n),
      .za_data        (sdram_s1_readdata),
      .za_valid       (sdram_s1_readdatavalid),
      .za_waitrequest (sdram_s1_waitrequest),
      .zs_addr        (zs_addr_from_the_sdram),
      .zs_ba          (zs_ba_from_the_sdram),
      .zs_cas_n       (zs_cas_n_from_the_sdram),
      .zs_cke         (zs_cke_from_the_sdram),
      .zs_cs_n        (zs_cs_n_from_the_sdram),
      .zs_dq          (zs_dq_to_and_from_the_sdram),
      .zs_dqm         (zs_dqm_from_the_sdram),
      .zs_ras_n       (zs_ras_n_from_the_sdram),
      .zs_we_n        (zs_we_n_from_the_sdram)
    );

  sram_cpu_ctrl_arbitrator the_sram_cpu_ctrl
    (
      .clk                                                            (clk_sys),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_byteenable_sram_cpu_ctrl                       (cpu_data_master_byteenable_sram_cpu_ctrl),
      .cpu_data_master_dbs_address                                    (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                   (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_sram_cpu_ctrl                          (cpu_data_master_granted_sram_cpu_ctrl),
      .cpu_data_master_latency_counter                                (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_sram_cpu_ctrl                (cpu_data_master_qualified_request_sram_cpu_ctrl),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register        (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_sram_cpu_ctrl                  (cpu_data_master_read_data_valid_sram_cpu_ctrl),
      .cpu_data_master_requests_sram_cpu_ctrl                         (cpu_data_master_requests_sram_cpu_ctrl),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                             (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_sram_cpu_ctrl                   (cpu_instruction_master_granted_sram_cpu_ctrl),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_sram_cpu_ctrl         (cpu_instruction_master_qualified_request_sram_cpu_ctrl),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_read_data_valid_sram_cpu_ctrl           (cpu_instruction_master_read_data_valid_sram_cpu_ctrl),
      .cpu_instruction_master_requests_sram_cpu_ctrl                  (cpu_instruction_master_requests_sram_cpu_ctrl),
      .d1_sram_cpu_ctrl_end_xfer                                      (d1_sram_cpu_ctrl_end_xfer),
      .reset_n                                                        (clk_sys_reset_n),
      .sram_cpu_ctrl_address                                          (sram_cpu_ctrl_address),
      .sram_cpu_ctrl_byteenable_n                                     (sram_cpu_ctrl_byteenable_n),
      .sram_cpu_ctrl_chipselect_n                                     (sram_cpu_ctrl_chipselect_n),
      .sram_cpu_ctrl_read_n                                           (sram_cpu_ctrl_read_n),
      .sram_cpu_ctrl_readdata                                         (sram_cpu_ctrl_readdata),
      .sram_cpu_ctrl_readdata_from_sa                                 (sram_cpu_ctrl_readdata_from_sa),
      .sram_cpu_ctrl_reset                                            (sram_cpu_ctrl_reset),
      .sram_cpu_ctrl_write_n                                          (sram_cpu_ctrl_write_n),
      .sram_cpu_ctrl_writedata                                        (sram_cpu_ctrl_writedata)
    );

  sram the_sram
    (
      .address      (sram_cpu_ctrl_address),
      .byteenable_n (sram_cpu_ctrl_byteenable_n),
      .chipselect_n (sram_cpu_ctrl_chipselect_n),
      .clk          (clk_sys),
      .read_n       (sram_cpu_ctrl_read_n),
      .readdata     (sram_cpu_ctrl_readdata),
      .reset        (sram_cpu_ctrl_reset),
      .sram_addr    (sram_addr_from_the_sram),
      .sram_ce_n    (sram_ce_n_from_the_sram),
      .sram_dq      (sram_dq_to_and_from_the_sram),
      .sram_lb_n    (sram_lb_n_from_the_sram),
      .sram_oe_n    (sram_oe_n_from_the_sram),
      .sram_ub_n    (sram_ub_n_from_the_sram),
      .sram_we_n    (sram_we_n_from_the_sram),
      .write_n      (sram_cpu_ctrl_write_n),
      .writedata    (sram_cpu_ctrl_writedata)
    );

  sseg_s1_arbitrator the_sseg_s1
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_sseg_s1                         (cpu_data_master_granted_sseg_s1),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_sseg_s1               (cpu_data_master_qualified_request_sseg_s1),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_sseg_s1                 (cpu_data_master_read_data_valid_sseg_s1),
      .cpu_data_master_requests_sseg_s1                        (cpu_data_master_requests_sseg_s1),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .cpu_data_master_writedata                               (cpu_data_master_writedata),
      .d1_sseg_s1_end_xfer                                     (d1_sseg_s1_end_xfer),
      .reset_n                                                 (clk_sys_reset_n),
      .sseg_s1_address                                         (sseg_s1_address),
      .sseg_s1_chipselect                                      (sseg_s1_chipselect),
      .sseg_s1_readdata                                        (sseg_s1_readdata),
      .sseg_s1_readdata_from_sa                                (sseg_s1_readdata_from_sa),
      .sseg_s1_reset_n                                         (sseg_s1_reset_n),
      .sseg_s1_write_n                                         (sseg_s1_write_n),
      .sseg_s1_writedata                                       (sseg_s1_writedata)
    );

  sseg the_sseg
    (
      .address    (sseg_s1_address),
      .chipselect (sseg_s1_chipselect),
      .clk        (clk_sys),
      .out_port   (out_port_from_the_sseg),
      .readdata   (sseg_s1_readdata),
      .reset_n    (sseg_s1_reset_n),
      .write_n    (sseg_s1_write_n),
      .writedata  (sseg_s1_writedata)
    );

  switch_s1_arbitrator the_switch_s1
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_switch_s1                       (cpu_data_master_granted_switch_s1),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_switch_s1             (cpu_data_master_qualified_request_switch_s1),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_switch_s1               (cpu_data_master_read_data_valid_switch_s1),
      .cpu_data_master_requests_switch_s1                      (cpu_data_master_requests_switch_s1),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .d1_switch_s1_end_xfer                                   (d1_switch_s1_end_xfer),
      .reset_n                                                 (clk_sys_reset_n),
      .switch_s1_address                                       (switch_s1_address),
      .switch_s1_readdata                                      (switch_s1_readdata),
      .switch_s1_readdata_from_sa                              (switch_s1_readdata_from_sa),
      .switch_s1_reset_n                                       (switch_s1_reset_n)
    );

  switch the_switch
    (
      .address  (switch_s1_address),
      .clk      (clk_sys),
      .in_port  (in_port_to_the_switch),
      .readdata (switch_s1_readdata),
      .reset_n  (switch_s1_reset_n)
    );

  sys_timer_s1_arbitrator the_sys_timer_s1
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_sys_timer_s1                    (cpu_data_master_granted_sys_timer_s1),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_sys_timer_s1          (cpu_data_master_qualified_request_sys_timer_s1),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_sys_timer_s1            (cpu_data_master_read_data_valid_sys_timer_s1),
      .cpu_data_master_requests_sys_timer_s1                   (cpu_data_master_requests_sys_timer_s1),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .cpu_data_master_writedata                               (cpu_data_master_writedata),
      .d1_sys_timer_s1_end_xfer                                (d1_sys_timer_s1_end_xfer),
      .reset_n                                                 (clk_sys_reset_n),
      .sys_timer_s1_address                                    (sys_timer_s1_address),
      .sys_timer_s1_chipselect                                 (sys_timer_s1_chipselect),
      .sys_timer_s1_irq                                        (sys_timer_s1_irq),
      .sys_timer_s1_irq_from_sa                                (sys_timer_s1_irq_from_sa),
      .sys_timer_s1_readdata                                   (sys_timer_s1_readdata),
      .sys_timer_s1_readdata_from_sa                           (sys_timer_s1_readdata_from_sa),
      .sys_timer_s1_reset_n                                    (sys_timer_s1_reset_n),
      .sys_timer_s1_write_n                                    (sys_timer_s1_write_n),
      .sys_timer_s1_writedata                                  (sys_timer_s1_writedata)
    );

  sys_timer the_sys_timer
    (
      .address    (sys_timer_s1_address),
      .chipselect (sys_timer_s1_chipselect),
      .clk        (clk_sys),
      .irq        (sys_timer_s1_irq),
      .readdata   (sys_timer_s1_readdata),
      .reset_n    (sys_timer_s1_reset_n),
      .write_n    (sys_timer_s1_write_n),
      .writedata  (sys_timer_s1_writedata)
    );

  sysid_control_slave_arbitrator the_sysid_control_slave
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_sysid_control_slave             (cpu_data_master_granted_sysid_control_slave),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_sysid_control_slave   (cpu_data_master_qualified_request_sysid_control_slave),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_sysid_control_slave     (cpu_data_master_read_data_valid_sysid_control_slave),
      .cpu_data_master_requests_sysid_control_slave            (cpu_data_master_requests_sysid_control_slave),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .d1_sysid_control_slave_end_xfer                         (d1_sysid_control_slave_end_xfer),
      .reset_n                                                 (clk_sys_reset_n),
      .sysid_control_slave_address                             (sysid_control_slave_address),
      .sysid_control_slave_readdata                            (sysid_control_slave_readdata),
      .sysid_control_slave_readdata_from_sa                    (sysid_control_slave_readdata_from_sa),
      .sysid_control_slave_reset_n                             (sysid_control_slave_reset_n)
    );

  sysid the_sysid
    (
      .address  (sysid_control_slave_address),
      .clock    (sysid_control_slave_clock),
      .readdata (sysid_control_slave_readdata),
      .reset_n  (sysid_control_slave_reset_n)
    );

  usr_timer_s1_arbitrator the_usr_timer_s1
    (
      .clk                                                     (clk_sys),
      .cpu_data_master_address_to_slave                        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_usr_timer_s1                    (cpu_data_master_granted_usr_timer_s1),
      .cpu_data_master_latency_counter                         (cpu_data_master_latency_counter),
      .cpu_data_master_qualified_request_usr_timer_s1          (cpu_data_master_qualified_request_usr_timer_s1),
      .cpu_data_master_read                                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_usr_timer_s1            (cpu_data_master_read_data_valid_usr_timer_s1),
      .cpu_data_master_requests_usr_timer_s1                   (cpu_data_master_requests_usr_timer_s1),
      .cpu_data_master_write                                   (cpu_data_master_write),
      .cpu_data_master_writedata                               (cpu_data_master_writedata),
      .d1_usr_timer_s1_end_xfer                                (d1_usr_timer_s1_end_xfer),
      .reset_n                                                 (clk_sys_reset_n),
      .usr_timer_s1_address                                    (usr_timer_s1_address),
      .usr_timer_s1_chipselect                                 (usr_timer_s1_chipselect),
      .usr_timer_s1_irq                                        (usr_timer_s1_irq),
      .usr_timer_s1_irq_from_sa                                (usr_timer_s1_irq_from_sa),
      .usr_timer_s1_readdata                                   (usr_timer_s1_readdata),
      .usr_timer_s1_readdata_from_sa                           (usr_timer_s1_readdata_from_sa),
      .usr_timer_s1_reset_n                                    (usr_timer_s1_reset_n),
      .usr_timer_s1_write_n                                    (usr_timer_s1_write_n),
      .usr_timer_s1_writedata                                  (usr_timer_s1_writedata)
    );

  usr_timer the_usr_timer
    (
      .address    (usr_timer_s1_address),
      .chipselect (usr_timer_s1_chipselect),
      .clk        (clk_sys),
      .irq        (usr_timer_s1_irq),
      .readdata   (usr_timer_s1_readdata),
      .reset_n    (usr_timer_s1_reset_n),
      .write_n    (usr_timer_s1_write_n),
      .writedata  (usr_timer_s1_writedata)
    );

  //reset is asserted asynchronously and deasserted synchronously
  nios_sd_card_reset_clk_sys_domain_synch_module nios_sd_card_reset_clk_sys_domain_synch
    (
      .clk      (clk_sys),
      .data_in  (1'b1),
      .data_out (clk_sys_reset_n),
      .reset_n  (reset_n_sources)
    );

  //reset sources mux, which is an e_mux
  assign reset_n_sources = ~(~reset_n |
    0 |
    cpu_jtag_debug_module_resetrequest_from_sa |
    cpu_jtag_debug_module_resetrequest_from_sa |
    0);

  //reset is asserted asynchronously and deasserted synchronously
  nios_sd_card_reset_clk_50M_domain_synch_module nios_sd_card_reset_clk_50M_domain_synch
    (
      .clk      (clk_50M),
      .data_in  (1'b1),
      .data_out (clk_50M_reset_n),
      .reset_n  (reset_n_sources)
    );

  //nios_sd_card_clock_0_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  assign nios_sd_card_clock_0_out_endofpacket = 0;

  //sysid_control_slave_clock of type clock does not connect to anything so wire it to default (0)
  assign sysid_control_slave_clock = 0;


endmodule


//synthesis translate_off



// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

// AND HERE WILL BE PRESERVED </ALTERA_NOTE>


// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above

// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif

`include "c:/altera/11.1sp1/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/11.1sp1/quartus/eda/sim_lib/220model.v"
`include "c:/altera/11.1sp1/quartus/eda/sim_lib/sgate.v"
`include "pll.vo"
`include "C:/Kempert/EEC693_NIOS/dlk_ip/dlk_avalon_sram/dlk_avalon_sram.v"
`include "sram.v"
`include "C:/Kempert/EEC693_NIOS/dlk_ip/dlk_spi/dlk_avalon_sd.v"
`include "C:/Kempert/EEC693_NIOS/dlk_ip/dlk_spi/dlk_spi.v"
`include "sd_card.v"
`include "ledg.v"
`include "sdram.v"
`include "sysid.v"
`include "btn.v"
`include "sys_timer.v"
`include "jtag_uart.v"
`include "cpu_test_bench.v"
`include "cpu_mult_cell.v"
`include "cpu_oci_test_bench.v"
`include "cpu_jtag_debug_module_tck.v"
`include "cpu_jtag_debug_module_sysclk.v"
`include "cpu_jtag_debug_module_wrapper.v"
`include "cpu.v"
`include "usr_timer.v"
`include "ledr.v"
`include "onchip_mem.v"
`include "switch.v"
`include "nios_sd_card_clock_0.v"
`include "sseg.v"

`timescale 1ns / 1ps

module test_bench 
;


  wire             areset_to_the_pll;
  wire             clk;
  reg              clk_50M;
  wire             clk_sdram;
  wire             clk_sys;
  wire    [  3: 0] in_port_to_the_btn;
  wire    [  9: 0] in_port_to_the_switch;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire             locked_from_the_pll;
  wire             nios_sd_card_clock_0_in_endofpacket_from_sa;
  wire             nios_sd_card_clock_0_out_endofpacket;
  wire    [  1: 0] nios_sd_card_clock_0_out_nativeaddress;
  wire    [  7: 0] out_port_from_the_ledg;
  wire    [  9: 0] out_port_from_the_ledr;
  wire    [ 31: 0] out_port_from_the_sseg;
  wire             phasedone_from_the_pll;
  reg              reset_n;
  wire             sd_clk_from_the_sd_card;
  wire             sd_cs_from_the_sd_card;
  wire             sd_di_from_the_sd_card;
  wire             sd_do_to_the_sd_card;
  wire    [ 17: 0] sram_addr_from_the_sram;
  wire             sram_ce_n_from_the_sram;
  wire    [ 15: 0] sram_dq_to_and_from_the_sram;
  wire             sram_lb_n_from_the_sram;
  wire             sram_oe_n_from_the_sram;
  wire             sram_ub_n_from_the_sram;
  wire             sram_we_n_from_the_sram;
  wire             sysid_control_slave_clock;
  wire    [ 11: 0] zs_addr_from_the_sdram;
  wire    [  1: 0] zs_ba_from_the_sdram;
  wire             zs_cas_n_from_the_sdram;
  wire             zs_cke_from_the_sdram;
  wire             zs_cs_n_from_the_sdram;
  wire    [ 15: 0] zs_dq_to_and_from_the_sdram;
  wire    [  1: 0] zs_dqm_from_the_sdram;
  wire             zs_ras_n_from_the_sdram;
  wire             zs_we_n_from_the_sdram;


// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
//  add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>

  //Set us up the Dut
  nios_sd_card DUT
    (
      .areset_to_the_pll            (areset_to_the_pll),
      .clk_50M                      (clk_50M),
      .clk_sdram                    (clk_sdram),
      .clk_sys                      (clk_sys),
      .in_port_to_the_btn           (in_port_to_the_btn),
      .in_port_to_the_switch        (in_port_to_the_switch),
      .locked_from_the_pll          (locked_from_the_pll),
      .out_port_from_the_ledg       (out_port_from_the_ledg),
      .out_port_from_the_ledr       (out_port_from_the_ledr),
      .out_port_from_the_sseg       (out_port_from_the_sseg),
      .phasedone_from_the_pll       (phasedone_from_the_pll),
      .reset_n                      (reset_n),
      .sd_clk_from_the_sd_card      (sd_clk_from_the_sd_card),
      .sd_cs_from_the_sd_card       (sd_cs_from_the_sd_card),
      .sd_di_from_the_sd_card       (sd_di_from_the_sd_card),
      .sd_do_to_the_sd_card         (sd_do_to_the_sd_card),
      .sram_addr_from_the_sram      (sram_addr_from_the_sram),
      .sram_ce_n_from_the_sram      (sram_ce_n_from_the_sram),
      .sram_dq_to_and_from_the_sram (sram_dq_to_and_from_the_sram),
      .sram_lb_n_from_the_sram      (sram_lb_n_from_the_sram),
      .sram_oe_n_from_the_sram      (sram_oe_n_from_the_sram),
      .sram_ub_n_from_the_sram      (sram_ub_n_from_the_sram),
      .sram_we_n_from_the_sram      (sram_we_n_from_the_sram),
      .zs_addr_from_the_sdram       (zs_addr_from_the_sdram),
      .zs_ba_from_the_sdram         (zs_ba_from_the_sdram),
      .zs_cas_n_from_the_sdram      (zs_cas_n_from_the_sdram),
      .zs_cke_from_the_sdram        (zs_cke_from_the_sdram),
      .zs_cs_n_from_the_sdram       (zs_cs_n_from_the_sdram),
      .zs_dq_to_and_from_the_sdram  (zs_dq_to_and_from_the_sdram),
      .zs_dqm_from_the_sdram        (zs_dqm_from_the_sdram),
      .zs_ras_n_from_the_sdram      (zs_ras_n_from_the_sdram),
      .zs_we_n_from_the_sdram       (zs_we_n_from_the_sdram)
    );

  initial
    clk_50M = 1'b0;
  always
    #10 clk_50M <= ~clk_50M;
  
  initial 
    begin
      reset_n <= 0;
      #200 reset_n <= 1;
    end

endmodule


//synthesis translate_on