nios_sd_card |

2013.07.09.11:36:53 | Datasheet

Overview

clk_50M | nios_sd_card
| ledg
| out_port
| out_port
| out_port
| in_port
| in_port

Processor
cpu Nios II 11.1
All Components
cpu altera_nios2 11.1
ledg altera_avalon_pio 11.1
ledr altera_avalon_pio 11.1
sseg altera_avalon_pio 11.1
switch altera_avalon_pio 11.1
btn altera_avalon_pio 11.1
sys_timer altera_avalon_timer 11.1
usr_timer altera_avalon_timer 11.1
jtag_uart altera_avalon_jtag_uart 11.1
sysid altera_avalon_sysid 11.1
sram dlk_avalon_sram 1.0
onchip_mem altera_avalon_onchip_memory2 11.1
sdram altera_avalon_new_sdram_controller 11.1
pll altpll 11.1
sd_card dlk_avalon_sd 1.0
Memory Map

| cpu
instruction_master | data_master
cpu |  |
jtag_debug_module | 0x01108800 | 0x01108800
ledg |  |
s1 |  | 0x01109040
ledr |  |
s1 |  | 0x01109050
sseg |  |
s1 |  | 0x01109060
switch |  |
s1 |  | 0x01109070
btn |  |
s1 |  | 0x01109080
sys_timer |  |
s1 |  | 0x01109000
usr_timer |  |
s1 |  | 0x01109020
jtag_uart |  |
avalon_jtag_slave |  | 0x011090b0
sysid |  |
control_slave |  | 0x011090b8
sram |  |
cpu_ctrl | 0x00100000 | 0x00100000
onchip_mem |  |
s1 | 0x00000000 | 0x00000000
sdram |  |
s1 | 0x00800000 | 0x00800000
pll |  |
pll_slave |  | 0x01109090
sd_card |  |
cpu_ctrl |  | 0x011090a0

## clk_50M

clock_source v11.1

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## cpu

altera_nios2 v11.1

pll | c0 | cpu
clk
|  | data_master | ledg
|  | s1
|  | data_master | ledr
|  | s1
|  | data_master | sseg
|  | s1
|  | data_master | switch
|  | s1
|  | data_master | btn
|  | s1
|  | d_irq
|  | irq
|  | data_master | sys_timer
|  | s1
|  | d_irq
|  | irq
|  | data_master | usr_timer
|  | s1
|  | d_irq
|  | irq
|  | data_master | jtag_uart
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | sysid
|  | control_slave
|  | instruction_master | sram
|  | cpu_ctrl
|  | data_master
|  | cpu_ctrl
|  | instruction_master | onchip_mem
|  | s1
|  | data_master
|  | s1
|  | instruction_master | sdram
|  | s1
|  | data_master
|  | s1
|  | data_master | pll
|  | pll_slave
|  | data_master | sd_card
|  | cpu_ctrl

## Parameters
userDefinedSettings |
tightlyCoupledInstructionMaster3MapParam |
tightlyCoupledInstructionMaster3AddrWidth | 1
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledDataMaster3MapParam |
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster0AddrWidth | 1
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSets | 0
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_interruptControllerType | Internal
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Automatic
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | onchip_mem.s1
resetOffset | 0
muldiv_multiplierType | EmbeddedMulFast
muldiv_divider | false
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _4
mmu_udtlbNumEntries | _6
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _8
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
internalIrqMaskSystemInfo | 30
instSlaveMapParam | <address-map><slave name='onchip_mem.s1' start='0x0' end='0x800' /><slave name='sram.cpu_ctrl' start='0x100000' end='0x180000' /><slave name='sdram.s1' start='0x800000' end='0x1000000' /><slave name='cpu.jtag_debug_module' start='0x1108800' end='0x1109000' /></address-map>
instAddrWidth | 25
impl | Fast
icache_size | _16384
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | None
exceptionSlave | onchip_mem.s1
exceptionOffset | 32
deviceFeaturesSystemInfo | ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
deviceFamilyName | Cyclone II
debug_triggerArming | true
debug_level | Level1
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _2048
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _32
dcache_bursts | false
dataSlaveMapParam | <address-map><slave name='onchip_mem.s1' start='0x0' end='0x800' /><slave name='sram.cpu_ctrl' start='0x100000' end='0x180000' /><slave name='sdram.s1' start='0x800000' end='0x1000000' /><slave name='cpu.jtag_debug_module' start='0x1108800' end='0x1109000' /><slave name='sys_timer.s1' start='0x1109000' end='0x1109020' /><slave name='usr_timer.s1' start='0x1109020' end='0x1109040' /><slave name='ledg.s1' start='0x1109040' end='0x1109050' /><slave name='ledr.s1' start='0x1109050' end='0x1109060' /><slave name='sseg.s1' start='0x1109060' end='0x1109070' /><slave name='switch.s1' start='0x1109070' end='0x1109080' /><slave name='btn.s1' start='0x1109080' end='0x1109090' /><slave name='pll.pll_slave' start='0x1109090' end='0x11090A0' /><slave name='sd_card.cpu_ctrl' start='0x11090A0' end='0x11090B0' /><slave name='jtag_uart.avalon_jtag_slave' start='0x11090B0' end='0x11090B8' /><slave name='sysid.control_slave' start='0x11090B8' end='0x11090C0' /></address-map>
dataAddrWidth | 25
customInstSlavesSystemInfo | <info/>
cpuReset | false
cpuID | 0
clockFrequency | 50000000
breakSlave | cpu.jtag_debug_module
breakOffset | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
CPU_IMPLEMENTATION | "fast"
BIG_ENDIAN | 0
CPU_FREQ | 50000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 16384
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
INITDA_SUPPORTED |
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x20
RESET_ADDR | 0x0
BREAK_ADDR | 0x1108820
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
INST_ADDR_WIDTH | 25
DATA_ADDR_WIDTH | 25
NUM_OF_SHADOW_REG_SETS | 0

## ledg

altera_avalon_pio v11.1

cpu | data_master | ledg
s1
pll | c0
clk

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 8
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## ledr

altera_avalon_pio v11.1

cpu | data_master | ledr
s1
pll | c0
clk

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 10
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 10
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## sseg

altera_avalon_pio v11.1

cpu | data_master | sseg
s1
pll | c0
clk

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 32
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## switch

altera_avalon_pio v11.1

cpu | data_master | switch
s1
pll | c0
clk

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 10
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 10
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## btn

altera_avalon_pio v11.1

cpu | data_master | btn
s1
d_irq
irq
pll | c0
clk

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 50000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 4
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 50000000u

## sys_timer

altera_avalon_timer v11.1

cpu | data_master | sys_timer
s1
d_irq
irq
pll | c0
clk

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 50000000
timeoutPulseOutput | false
timerPreset | FULL_FEATURED
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 50000000u
LOAD_VALUE | 49999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## usr_timer

altera_avalon_timer v11.1

cpu | data_master | usr_timer
s1
d_irq
irq
pll | c0
clk

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 50000000
timeoutPulseOutput | false
timerPreset | FULL_FEATURED
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 50000000u
LOAD_VALUE | 49999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## jtag_uart

altera_avalon_jtag_uart v11.1

cpu | data_master | jtag_uart
avalon_jtag_slave
d_irq
irq
pll | c0
clk

## Parameters
allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
WRITE_DEPTH | 64
READ_DEPTH | 64
WRITE_THRESHOLD | 8
READ_THRESHOLD | 8

## sysid

altera_avalon_sysid v11.1

cpu | data_master | sysid
control_slave
pll | c0
clk

## Parameters
id | 0
timestamp | 1373384198
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ID | 0u
TIMESTAMP | 1373384198u

## sram

dlk_avalon_sram v1.0

cpu | instruction_master | sram
cpu_ctrl
data_master
cpu_ctrl
pll | c0
clock

## Parameters
AUTO_CLOCK_CLOCK_RATE | 50000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## onchip_mem

altera_avalon_onchip_memory2 v11.1

cpu | instruction_master | onchip_mem
s1
data_master
s1
pll | c0
clk1

## Parameters
allowInSystemMemoryContentEditor | false
autoInitializationFileName | onchip_mem
blockType | AUTO
dataWidth | 32
deviceFamily | Cyclone II
dualPort | false
initMemContent | true
initializationFileName | onchip_mem
instanceID | NONE
memorySize | 2048
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
generateLegacySim | false

## Software Assignments
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
INIT_CONTENTS_FILE | "onchip_mem"
NON_DEFAULT_INIT_FILE_ENABLED | 0
GUI_RAM_BLOCK_TYPE | "Automatic"
WRITABLE | 1
DUAL_PORT | 0
SINGLE_CLOCK_OP | 0
SIZE_VALUE | 2048u
SIZE_MULTIPLE | 1
CONTENTS_INFO | ""
RAM_BLOCK_TYPE | "Auto"
INIT_MEM_CONTENT | 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
INSTANCE_ID | "NONE"
READ_DURING_WRITE_MODE | "DONT_CARE"

## sdram

altera_avalon_new_sdram_controller v11.1

cpu | instruction_master | sdram
s1
data_master
s1
pll | c0
clk

## Parameters
TAC | 6.0
TMRD | 3
TRCD | 20.0
TRFC | 70.0
TRP | 20.0
TWR | 14.0
casLatency | 3
clockRate | 50000000
columnWidth | 8
dataWidth | 16
generateSimulationModel | false
initNOPDelay | 0.0
initRefreshCommands | 8
masteredTristateBridgeSlave |
model | custom
numberOfBanks | 4
numberOfChipSelects | 1
pinsSharedViaTriState | false
powerUpDelay | 200.0
refreshPeriod | 15.625
registerDataIn | true
rowWidth | 12
size | 8388608
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
REGISTER_DATA_IN | 1
SIM_MODEL_BASE | 0
SDRAM_DATA_WIDTH | 16
SDRAM_ADDR_WIDTH | 22
SDRAM_ROW_WIDTH | 12
SDRAM_COL_WIDTH | 8
SDRAM_NUM_CHIPSELECTS | 1
SDRAM_NUM_BANKS | 4
REFRESH_PERIOD | 15.625
POWERUP_DELAY | 200.0
CAS_LATENCY | 3
T_RFC | 70.0
T_RP | 20.0
T_MRD | 3
T_RCD | 20.0
T_AC | 6.0
T_WR | 14.0
INIT_REFRESH_COMMANDS | 8
INIT_NOP_DELAY | 0.0
SHARED_DATA | 0
STARVATION_INDICATOR | 0
TRISTATE_BRIDGE_SLAVE | ""
IS_INITIALIZED | 1
SDRAM_BANK_WIDTH | 2
CONTENTS_INFO | ""

## pll

altpll v11.1

cpu | data_master | pll
pll_slave
clk_50M | clk
inclk_interface
|  | c0 | sdram
|  | clk
|  | c0 | onchip_mem
|  | clk1
|  | c0 | sram
|  | clock
|  | c0 | sysid
|  | clk
|  | c0 | jtag_uart
|  | clk
|  | c0 | usr_timer
|  | clk
|  | c0 | sys_timer
|  | clk
|  | c0 | switch
|  | clk
|  | c0 | sseg
|  | clk
|  | c0 | ledr
|  | clk
|  | c0 | ledg
|  | clk
|  | c0 | cpu
|  | clk
|  | c0 | sd_card
|  | clock
|  | c0 | btn
|  | clk

## Parameters
HIDDEN_CUSTOM_ELABORATION | altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT | altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY | Cyclone II
WIDTH_CLOCK |
WIDTH_PHASECOUNTERSELECT |
PRIMARY_CLOCK |
INCLK0_INPUT_FREQUENCY | 20000
INCLK1_INPUT_FREQUENCY |
OPERATION_MODE | NORMAL
PLL_TYPE |
QUALIFY_CONF_DONE |
COMPENSATE_CLOCK | CLK0
SCAN_CHAIN |
GATE_LOCK_SIGNAL | NO
GATE_LOCK_COUNTER |
LOCK_HIGH |
LOCK_LOW |
VALID_LOCK_MULTIPLIER | 1
INVALID_LOCK_MULTIPLIER | 5
SWITCH_OVER_ON_LOSSCLK |
SWITCH_OVER_ON_GATED_LOCK |
ENABLE_SWITCH_OVER_COUNTER |
SKIP_VCO |
SWITCH_OVER_COUNTER |
SWITCH_OVER_TYPE |
FEEDBACK_SOURCE |
BANDWIDTH |
BANDWIDTH_TYPE |
SPREAD_FREQUENCY |
DOWN_SPREAD |
SELF_RESET_ON_GATED_LOSS_LOCK |
SELF_RESET_ON_LOSS_LOCK |
CLK0_MULTIPLY_BY | 1
CLK1_MULTIPLY_BY | 1
CLK2_MULTIPLY_BY |
CLK3_MULTIPLY_BY |
CLK4_MULTIPLY_BY |
CLK5_MULTIPLY_BY |
CLK6_MULTIPLY_BY |
CLK7_MULTIPLY_BY |
CLK8_MULTIPLY_BY |
CLK9_MULTIPLY_BY |
EXTCLK0_MULTIPLY_BY |
EXTCLK1_MULTIPLY_BY |
EXTCLK2_MULTIPLY_BY |
EXTCLK3_MULTIPLY_BY |
CLK0_DIVIDE_BY | 1
CLK1_DIVIDE_BY | 1
CLK2_DIVIDE_BY |
CLK3_DIVIDE_BY |
CLK4_DIVIDE_BY |
CLK5_DIVIDE_BY |
CLK6_DIVIDE_BY |
CLK7_DIVIDE_BY |
CLK8_DIVIDE_BY |
CLK9_DIVIDE_BY |
EXTCLK0_DIVIDE_BY |
EXTCLK1_DIVIDE_BY |
EXTCLK2_DIVIDE_BY |
EXTCLK3_DIVIDE_BY |
CLK0_PHASE_SHIFT | 0
CLK1_PHASE_SHIFT | -3000
CLK2_PHASE_SHIFT |
CLK3_PHASE_SHIFT |
CLK4_PHASE_SHIFT |
CLK5_PHASE_SHIFT |
CLK6_PHASE_SHIFT |
CLK7_PHASE_SHIFT |
CLK8_PHASE_SHIFT |
CLK9_PHASE_SHIFT |
EXTCLK0_PHASE_SHIFT |
EXTCLK1_PHASE_SHIFT |
EXTCLK2_PHASE_SHIFT |
EXTCLK3_PHASE_SHIFT |
CLK0_DUTY_CYCLE | 50
CLK1_DUTY_CYCLE | 50
CLK2_DUTY_CYCLE |
CLK3_DUTY_CYCLE |
CLK4_DUTY_CYCLE |
CLK5_DUTY_CYCLE |
CLK6_DUTY_CYCLE |
CLK7_DUTY_CYCLE |
CLK8_DUTY_CYCLE |
CLK9_DUTY_CYCLE |
EXTCLK0_DUTY_CYCLE |
EXTCLK1_DUTY_CYCLE |
EXTCLK2_DUTY_CYCLE |
EXTCLK3_DUTY_CYCLE |
PORT_clkena0 | PORT_UNUSED
PORT_clkena1 | PORT_UNUSED
PORT_clkena2 | PORT_UNUSED
PORT_clkena3 | PORT_UNUSED
PORT_clkena4 | PORT_UNUSED
PORT_clkena5 | PORT_UNUSED
PORT_extclkena0 |
PORT_extclkena1 |
PORT_extclkena2 |
PORT_extclkena3 |
PORT_extclk0 | PORT_UNUSED
PORT_extclk1 | PORT_UNUSED
PORT_extclk2 | PORT_UNUSED
PORT_extclk3 | PORT_UNUSED
PORT_CLKBAD0 | PORT_UNUSED
PORT_CLKBAD1 | PORT_UNUSED
PORT_clk0 | PORT_USED
PORT_clk1 | PORT_USED
PORT_clk2 | PORT_UNUSED
PORT_clk3 | PORT_UNUSED
PORT_clk4 | PORT_UNUSED
PORT_clk5 | PORT_UNUSED
PORT_clk6 |
PORT_clk7 |
PORT_clk8 |
PORT_clk9 |
PORT_SCANDATA | PORT_UNUSED
PORT_SCANDATAOUT | PORT_UNUSED
PORT_SCANDONE | PORT_UNUSED
PORT_SCLKOUT1 |
PORT_SCLKOUT0 |
PORT_ACTIVECLOCK | PORT_UNUSED
PORT_CLKLOSS | PORT_UNUSED
PORT_INCLK1 | PORT_UNUSED
PORT_INCLK0 | PORT_USED
PORT_FBIN | PORT_UNUSED
PORT_PLLENA | PORT_UNUSED
PORT_CLKSWITCH | PORT_UNUSED
PORT_ARESET | PORT_USED
PORT_PFDENA | PORT_UNUSED
PORT_SCANCLK | PORT_UNUSED
PORT_SCANACLR | PORT_UNUSED
PORT_SCANREAD | PORT_UNUSED
PORT_SCANWRITE | PORT_UNUSED
PORT_ENABLE0 |
PORT_ENABLE1 |
PORT_LOCKED | PORT_USED
PORT_CONFIGUPDATE | PORT_UNUSED
PORT_FBOUT |
PORT_PHASEDONE | PORT_UNUSED
PORT_PHASESTEP | PORT_UNUSED
PORT_PHASEUPDOWN | PORT_UNUSED
PORT_SCANCLKENA | PORT_UNUSED
PORT_PHASECOUNTERSELECT | PORT_UNUSED
PORT_VCOOVERRANGE |
PORT_VCOUNDERRANGE |
DPA_MULTIPLY_BY |
DPA_DIVIDE_BY |
DPA_DIVIDER |
VCO_MULTIPLY_BY |
VCO_DIVIDE_BY |
SCLKOUT0_PHASE_SHIFT |
SCLKOUT1_PHASE_SHIFT |
VCO_FREQUENCY_CONTROL |
VCO_PHASE_SHIFT_STEP |
USING_FBMIMICBIDIR_PORT |
SCAN_CHAIN_MIF_FILE |
AVALON_USE_SEPARATE_SYSCLK | NO
HIDDEN_CONSTANTS | CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#VALID_LOCK_MULTIPLIER 1 CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -3000 CT#PORT_ARESET PORT_USED CT#INVALID_LOCK_MULTIPLIER 5 CT#INTENDED_DEVICE_FAMILY {Cyclone II} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#GATE_LOCK_SIGNAL NO CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES | PT#GLOCKED_FEATURE_ENABLED 1 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 0 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 1 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 0 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_ENA_CHECK 0 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 0 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -3.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#BANDWIDTH_USE_CUSTOM 0 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone II} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1368808610011446.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS | UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC | IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#VALID_LOCK_MULTIPLIER 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#INVALID_LOCK_MULTIPLIER 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS | MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS | IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}
HIDDEN_IS_FIRST_EDIT | 0
AUTO_INCLK_INTERFACE_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## sd_card

dlk_avalon_sd v1.0

cpu | data_master | sd_card
cpu_ctrl
pll | c0
clock

## Parameters
AUTO_CLOCK_CLOCK_RATE | 50000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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