// sd.v

// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.

`timescale 1 ps / 1 ps
module sd (
		input  wire        clk,           //    clock.clk
		input  wire        reset,         //    reset.reset
		output wire        sd_cs,         //  ctrl_sd.export
		output wire        sd_clk,        //         .export
		output wire        sd_di,         //         .export
		input  wire        sd_do,         //         .export
		input  wire [1:0]  sd_address,    // cpu_ctrl.address
		input  wire        sd_chipselect, //         .chipselect
		input  wire        sd_write,      //         .write
		input  wire [31:0] sd_writedata,  //         .writedata
		output wire [31:0] sd_readdata    //         .readdata
	);

	dlk_avalon_sd sd (
		.clk           (clk),           //    clock.clk
		.reset         (reset),         //    reset.reset
		.sd_cs         (sd_cs),         //  ctrl_sd.export
		.sd_clk        (sd_clk),        //         .export
		.sd_di         (sd_di),         //         .export
		.sd_do         (sd_do),         //         .export
		.sd_address    (sd_address),    // cpu_ctrl.address
		.sd_chipselect (sd_chipselect), //         .chipselect
		.sd_write      (sd_write),      //         .write
		.sd_writedata  (sd_writedata),  //         .writedata
		.sd_readdata   (sd_readdata)    //         .readdata
	);

endmodule
