module sd_card_reader(
  input wire clk, reset,
  input wire [9:0] sw,
  input wire [3:0] key,
  output wire [7:0] ledg,
  output wire [9:0] ledr,
  output wire [6:0] hex3, hex2, hex1, hex0,

  // to/from SD CARD
  output wire sd_cs, sd_clk, sd_di,
  input wire sd_do,
  // to/from SRAM
  output wire [17:0] sram_addr,
  inout [15:0] sram_dq,
  output sram_ce_n, sram_oe_n, sram_we_n,
  output sram_lb_n, sram_ub_n,
  // to/from SDRAM
  output wire dram_clk,
  output wire dram_cs_n, dram_cke, dram_ldqm, dram_udqm,
  output wire dram_cas_n, dram_ras_n, dram_we_n,
  output wire [11:0] dram_addr,
  output wire dram_ba_0, dram_ba_1,
  inout wire [15:0] dram_dq
  );

  // signal declaration
  wire [31:0] sseg;

  // body
  // ===================================================================
  // instantiate nios
  // ===================================================================
  nios_sd_card nios_cpu_unit(
    .clk_50M(clk),
    .clk_sys(),
    .clk_sdram(dram_clk),
    .reset_n(1'b1),
    .in_port_to_the_switch(sw),
    .in_port_to_the_btn(key),
    .out_port_from_the_ledg(ledg),
    .out_port_from_the_ledr(ledr),
    .out_port_from_the_sseg(sseg),
    .sd_cs_from_the_sd_card(sd_cs),
    .sd_clk_from_the_sd_card(sd_clk),
    .sd_di_from_the_sd_card(sd_di),
    .sd_do_to_the_sd_card(sd_do),
    .sram_addr_from_the_sram(sram_addr),
    .sram_ce_n_from_the_sram(sram_ce_n),
    .sram_dq_to_and_from_the_sram(sram_dq),
    .sram_lb_n_from_the_sram(sram_lb_n),
    .sram_oe_n_from_the_sram(sram_oe_n),
    .sram_ub_n_from_the_sram(sram_ub_n),
    .sram_we_n_from_the_sram(sram_we_n),
    .zs_addr_from_the_sdram(dram_addr),
    .zs_ba_from_the_sdram({dram_ba_1, dram_ba_0}),
    .zs_cas_n_from_the_sdram(dram_cas_n),
    .zs_cke_from_the_sdram(dram_cke),
    .zs_cs_n_from_the_sdram(dram_cs_n),
    .zs_dq_to_and_from_the_sdram(dram_dq),
    .zs_dqm_from_the_sdram(dram_ldqm),
    .zs_ras_n_from_the_sdram(dram_ras_n),
    .zs_we_n_from_the_sdram(dram_we_n),
  );

  // ===================================================================
  // registers, write decoding, and read
  // ===================================================================
  // output assignment
  assign hex3 = sseg[30:24];
  assign hex2 = sseg[22:16];
  assign hex1 = sseg[14:8];
  assign hex0 = sseg[6:0];
endmodule
