--------------------------------------------------------------------------------
-- File Name: fifo7881.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1998 Free Model Foundation
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Munden 98 JUN 11 initial release
--
--------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: FIFO
-- Technology: TTL
-- Part: ACT7881
--
-- Desciption: 1K x 18 FIFO
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY fifo7881 IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_D0 : VitalDelayType01 := VitalZeroDelay01;
tipd_D1 : VitalDelayType01 := VitalZeroDelay01;
tipd_D2 : VitalDelayType01 := VitalZeroDelay01;
tipd_D3 : VitalDelayType01 := VitalZeroDelay01;
tipd_D4 : VitalDelayType01 := VitalZeroDelay01;
tipd_D5 : VitalDelayType01 := VitalZeroDelay01;
tipd_D6 : VitalDelayType01 := VitalZeroDelay01;
tipd_D7 : VitalDelayType01 := VitalZeroDelay01;
tipd_D8 : VitalDelayType01 := VitalZeroDelay01;
tipd_D9 : VitalDelayType01 := VitalZeroDelay01;
tipd_D10 : VitalDelayType01 := VitalZeroDelay01;
tipd_D11 : VitalDelayType01 := VitalZeroDelay01;
tipd_D12 : VitalDelayType01 := VitalZeroDelay01;
tipd_D13 : VitalDelayType01 := VitalZeroDelay01;
tipd_D14 : VitalDelayType01 := VitalZeroDelay01;
tipd_D15 : VitalDelayType01 := VitalZeroDelay01;
tipd_D16 : VitalDelayType01 := VitalZeroDelay01;
tipd_D17 : VitalDelayType01 := VitalZeroDelay01;
tipd_RSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WCLK : VitalDelayType01 := VitalZeroDelay01;
tipd_WEN1 : VitalDelayType01 := VitalZeroDelay01;
tipd_WEN2 : VitalDelayType01 := VitalZeroDelay01;
tipd_RCLK : VitalDelayType01 := VitalZeroDelay01;
tipd_REN1 : VitalDelayType01 := VitalZeroDelay01;
tipd_REN2 : VitalDelayType01 := VitalZeroDelay01;
tipd_OE : VitalDelayType01 := VitalZeroDelay01;
tipd_DAFNeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays: propagation delays
tpd_RSNeg_AF : VitalDelayType01:= UnitDelay01;
tpd_RSNeg_HF : VitalDelayType01:= UnitDelay01;
tpd_RSNeg_Q0 : VitalDelayType01Z:= UnitDelay01Z;
tpd_RCLK_Q0 : VitalDelayType01Z:= UnitDelay01Z;
tpd_OE_Q0 : VitalDelayType01Z:= UnitDelay01Z;
tpd_WCLK_IRF : VitalDelayType01 := UnitDelay01;
tpd_RCLK_ORF : VitalDelayType01 := UnitDelay01;
tpd_RCLK_AF : VitalDelayType01 := UnitDelay01;
tpd_RCLK_HF : VitalDelayType01 := UnitDelay01;
-- tpw values: pulse widths
tpw_RCLK_posedge : VitalDelayType := UnitDelay;
tpw_RCLK_negedge : VitalDelayType := UnitDelay;
tpw_WCLK_posedge : VitalDelayType := UnitDelay;
tpw_WCLK_negedge : VitalDelayType := UnitDelay;
tpw_RSNeg_negedge : VitalDelayType := UnitDelay;
tpw_DAFNeg_posedge : VitalDelayType := UnitDelay;
-- tperiod min (calculated as 1/max freq)
tperiod_RCLK_posedge : VitalDelayType := UnitDelay;
-- tsetup values: setup times
tsetup_D0_WCLK : VitalDelayType := UnitDelay;
tsetup_D0_DAFNeg : VitalDelayType := UnitDelay;
tsetup_WEN1_WCLK : VitalDelayType := UnitDelay;
tsetup_REN1_RCLK : VitalDelayType := UnitDelay;
tsetup_OE_RCLK : VitalDelayType := UnitDelay;
tsetup_RSNeg_RCLK : VitalDelayType := UnitDelay;
tsetup_DAFNeg_RSNeg : VitalDelayType := UnitDelay;
-- thold values: hold times
thold_D0_WCLK : VitalDelayType := UnitDelay;
thold_D0_DAFNeg : VitalDelayType := UnitDelay;
thold_WEN1_WCLK : VitalDelayType := UnitDelay;
thold_REN1_RCLK : VitalDelayType := UnitDelay;
thold_OE_RCLK : VitalDelayType := UnitDelay;
thold_RSNeg_RCLK : VitalDelayType := UnitDelay;
thold_DAFNeg_RSNeg : VitalDelayType := UnitDelay;
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXOn;
TimingModel : STRING := DefaultTimingModel
);
PORT (
D0 : IN std_logic := 'X'; -- Data Input Bus
D1 : IN std_logic := 'X';
D2 : IN std_logic := 'X';
D3 : IN std_logic := 'X';
D4 : IN std_logic := 'X';
D5 : IN std_logic := 'X';
D6 : IN std_logic := 'X';
D7 : IN std_logic := 'X';
D8 : IN std_logic := 'X';
D9 : IN std_logic := 'X';
D10 : IN std_logic := 'X';
D11 : IN std_logic := 'X';
D12 : IN std_logic := 'X';
D13 : IN std_logic := 'X';
D14 : IN std_logic := 'X';
D15 : IN std_logic := 'X';
D16 : IN std_logic := 'X';
D17 : IN std_logic := 'X';
RSNeg : IN std_logic := 'X'; -- Reset
WCLK : IN std_logic := 'X'; -- Write Clock
WEN1 : IN std_logic := 'X'; -- Write Enable
WEN2 : IN std_logic := 'X'; -- Write Enable
RCLK : IN std_logic := 'X'; -- Read Clock
REN1 : IN std_logic := 'X'; -- Read Enable
REN2 : IN std_logic := 'X'; -- Read Enable
OE : IN std_logic := 'X'; -- Output Enable
DAFNeg : IN std_logic := 'X'; -- Write Expansion Input
AF : OUT std_logic := 'U'; -- Programmable Almost Full/Empty Flag
HF : OUT std_logic := 'U'; -- Half-Full Flag
IRF : OUT std_logic := 'U'; -- Input Ready Flag
ORF : OUT std_logic := 'U'; -- Output Ready Flag
Q0 : OUT std_logic := 'U'; -- Data Output Bus
Q1 : OUT std_logic := 'U';
Q2 : OUT std_logic := 'U';
Q3 : OUT std_logic := 'U';
Q4 : OUT std_logic := 'U';
Q5 : OUT std_logic := 'U';
Q6 : OUT std_logic := 'U';
Q7 : OUT std_logic := 'U';
Q8 : OUT std_logic := 'U';
Q9 : OUT std_logic := 'U';
Q10 : OUT std_logic := 'U';
Q11 : OUT std_logic := 'U';
Q12 : OUT std_logic := 'U';
Q13 : OUT std_logic := 'U';
Q14 : OUT std_logic := 'U';
Q15 : OUT std_logic := 'U';
Q16 : OUT std_logic := 'U';
Q17 : OUT std_logic := 'U'
);
ATTRIBUTE VITAL_LEVEL0 OF fifo7881 : ENTITY IS TRUE;
END fifo7881;
--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF fifo7881 IS
ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;
TYPE statetype IS ARRAY (0 to 3) OF std_ulogic ;
TYPE mem_type IS ARRAY (0 to 1023 ) OF std_ulogic_vector(17 downto 0) ;
SIGNAL wordcount : INTEGER := 0 ;
SIGNAL D0_ipd : std_ulogic := 'X';
SIGNAL D1_ipd : std_ulogic := 'X';
SIGNAL D2_ipd : std_ulogic := 'X';
SIGNAL D3_ipd : std_ulogic := 'X';
SIGNAL D4_ipd : std_ulogic := 'X';
SIGNAL D5_ipd : std_ulogic := 'X';
SIGNAL D6_ipd : std_ulogic := 'X';
SIGNAL D7_ipd : std_ulogic := 'X';
SIGNAL D8_ipd : std_ulogic := 'X';
SIGNAL D9_ipd : std_ulogic := 'X';
SIGNAL D10_ipd : std_ulogic := 'X';
SIGNAL D11_ipd : std_ulogic := 'X';
SIGNAL D12_ipd : std_ulogic := 'X';
SIGNAL D13_ipd : std_ulogic := 'X';
SIGNAL D14_ipd : std_ulogic := 'X';
SIGNAL D15_ipd : std_ulogic := 'X';
SIGNAL D16_ipd : std_ulogic := 'X';
SIGNAL D17_ipd : std_ulogic := 'X';
SIGNAL RSNeg_ipd : std_ulogic := 'X';
SIGNAL WCLK_ipd : std_ulogic := 'X';
SIGNAL WEN1_ipd : std_ulogic := 'X';
SIGNAL WEN2_ipd : std_ulogic := 'X';
SIGNAL RCLK_ipd : std_ulogic := 'X';
SIGNAL REN1_ipd : std_ulogic := 'X';
SIGNAL REN2_ipd : std_ulogic := 'X';
SIGNAL OE_ipd : std_ulogic := 'X';
SIGNAL DAFNeg_ipd : std_ulogic := 'X';
SIGNAL Qout : std_ulogic_vector(17 downto 0) := (others => 'X');
BEGIN
----------------------------------------------------------------------------
-- Wire Delays
----------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1: VitalWireDelay (D0_ipd, D0, tipd_D0);
w_2: VitalWireDelay (D1_ipd, D1, tipd_D1);
w_3: VitalWireDelay (D2_ipd, D2, tipd_D2);
w_4: VitalWireDelay (D3_ipd, D3, tipd_D3);
w_5: VitalWireDelay (D4_ipd, D4, tipd_D4);
w_6: VitalWireDelay (D5_ipd, D5, tipd_D5);
w_7: VitalWireDelay (D6_ipd, D6, tipd_D6);
w_8: VitalWireDelay (D7_ipd, D7, tipd_D7);
w_9: VitalWireDelay (D8_ipd, D8, tipd_D8);
w_10: VitalWireDelay (D9_ipd, D9, tipd_D9);
w_11: VitalWireDelay (D10_ipd, D10, tipd_D10);
w_12: VitalWireDelay (D11_ipd, D11, tipd_D11);
w_13: VitalWireDelay (D12_ipd, D12, tipd_D12);
w_14: VitalWireDelay (D13_ipd, D13, tipd_D13);
w_15: VitalWireDelay (D14_ipd, D14, tipd_D14);
w_16: VitalWireDelay (D15_ipd, D15, tipd_D15);
w_17: VitalWireDelay (D16_ipd, D16, tipd_D16);
w_18: VitalWireDelay (D17_ipd, D17, tipd_D17);
w_19: VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);
w_20: VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
w_21: VitalWireDelay (WEN1_ipd, WEN1, tipd_WEN1);
w_22: VitalWireDelay (WEN2_ipd, WEN2, tipd_WEN2);
w_23: VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);
w_24: VitalWireDelay (REN1_ipd, REN1, tipd_REN1);
w_25: VitalWireDelay (REN2_ipd, REN2, tipd_REN2);
w_26: VitalWireDelay (OE_ipd, OE, tipd_OE);
w_27: VitalWireDelay (DAFNeg_ipd, DAFNeg, tipd_DAFNeg);
END BLOCK;
----------------------------------------------------------------------------
-- VITALBehavior Process
----------------------------------------------------------------------------
VITALBehavior1 : PROCESS(RSNeg_ipd, WCLK_ipd, RCLK_ipd, OE_ipd, REN1_ipd,
REN2_ipd, WEN1_ipd, WEN2_ipd, DAFNeg_ipd)
VARIABLE flagstate : statetype := "0000" ;
VARIABLE wordcounter : INTEGER := 0 ;
VARIABLE ae_offset : NATURAL := 0 ;
VARIABLE af_offset : NATURAL := 0 ;
VARIABLE d : std_logic_vector(17 downto 0) ;
VARIABLE d_temp : std_logic_vector(17 downto 0) ;
VARIABLE wrtclkcount : INTEGER := 0 ;
VARIABLE rdclkcount : INTEGER := 0 ;
VARIABLE i : INTEGER := 17 ;
VARIABLE rst : INTEGER := 2 ;
VARIABLE memory : mem_type ;
VARIABLE waddr : INTEGER := 0 ;
VARIABLE raddr : INTEGER := 0 ;
VARIABLE irflag : INTEGER := 2 ;
VARIABLE orflag : INTEGER := 2 ;
VARIABLE hf_limit : INTEGER := 0 ;
VARIABLE f_limit : INTEGER := 0 ;
VARIABLE ae_limit : INTEGER := 0 ;
VARIABLE af_limit : INTEGER := 0 ;
-- Timing Check Variables
VARIABLE Tviol_D0_WCLK : X01 := '0';
VARIABLE TD_D0_WCLK : VitalTimingDataType;
VARIABLE Tviol_D1_WCLK : X01 := '0';
VARIABLE TD_D1_WCLK : VitalTimingDataType;
VARIABLE Tviol_D2_WCLK : X01 := '0';
VARIABLE TD_D2_WCLK : VitalTimingDataType;
VARIABLE Tviol_D3_WCLK : X01 := '0';
VARIABLE TD_D3_WCLK : VitalTimingDataType;
VARIABLE Tviol_D4_WCLK : X01 := '0';
VARIABLE TD_D4_WCLK : VitalTimingDataType;
VARIABLE Tviol_D5_WCLK : X01 := '0';
VARIABLE TD_D5_WCLK : VitalTimingDataType;
VARIABLE Tviol_D6_WCLK : X01 := '0';
VARIABLE TD_D6_WCLK : VitalTimingDataType;
VARIABLE Tviol_D7_WCLK : X01 := '0';
VARIABLE TD_D7_WCLK : VitalTimingDataType;
VARIABLE Tviol_D8_WCLK : X01 := '0';
VARIABLE TD_D8_WCLK : VitalTimingDataType;
VARIABLE Tviol_D9_WCLK : X01 := '0';
VARIABLE TD_D9_WCLK : VitalTimingDataType;
VARIABLE Tviol_D10_WCLK : X01 := '0';
VARIABLE TD_D10_WCLK : VitalTimingDataType;
VARIABLE Tviol_D11_WCLK : X01 := '0';
VARIABLE TD_D11_WCLK : VitalTimingDataType;
VARIABLE Tviol_D12_WCLK : X01 := '0';
VARIABLE TD_D12_WCLK : VitalTimingDataType;
VARIABLE Tviol_D13_WCLK : X01 := '0';
VARIABLE TD_D13_WCLK : VitalTimingDataType;
VARIABLE Tviol_D14_WCLK : X01 := '0';
VARIABLE TD_D14_WCLK : VitalTimingDataType;
VARIABLE Tviol_D15_WCLK : X01 := '0';
VARIABLE TD_D15_WCLK : VitalTimingDataType;
VARIABLE Tviol_D16_WCLK : X01 := '0';
VARIABLE TD_D16_WCLK : VitalTimingDataType;
VARIABLE Tviol_D17_WCLK : X01 := '0';
VARIABLE TD_D17_WCLK : VitalTimingDataType;
VARIABLE Tviol_D0_DAFNeg: X01 := '0';
VARIABLE TD_D0_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D1_DAFNeg: X01 := '0';
VARIABLE TD_D1_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D2_DAFNeg: X01 := '0';
VARIABLE TD_D2_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D3_DAFNeg: X01 := '0';
VARIABLE TD_D3_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D4_DAFNeg: X01 := '0';
VARIABLE TD_D4_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D5_DAFNeg: X01 := '0';
VARIABLE TD_D5_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D6_DAFNeg: X01 := '0';
VARIABLE TD_D6_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D7_DAFNeg: X01 := '0';
VARIABLE TD_D7_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_D8_DAFNeg: X01 := '0';
VARIABLE TD_D8_DAFNeg : VitalTimingDataType;
VARIABLE Tviol_WEN1_WCLK : X01 := '0';
VARIABLE TD_WEN1_WCLK : VitalTimingDataType;
VARIABLE Tviol_WEN2_WCLK : X01 := '0';
VARIABLE TD_WEN2_WCLK : VitalTimingDataType;
VARIABLE Tviol_REN1_RCLK : X01 := '0';
VARIABLE TD_REN1_RCLK : VitalTimingDataType;
VARIABLE Tviol_REN2_RCLK : X01 := '0';
VARIABLE TD_REN2_RCLK : VitalTimingDataType;
VARIABLE Tviol_OE_RCLK : X01 := '0';
VARIABLE TD_OE_RCLK : VitalTimingDataType;
VARIABLE Tviol_RSNeg_RCLK : X01 := '0';
VARIABLE TD_RSNeg_RCLK : VitalTimingDataType;
VARIABLE Tviol_RSNeg_WCLK : X01 := '0';
VARIABLE TD_RSNeg_WCLK : VitalTimingDataType;
VARIABLE Tviol_DAFNeg_RSNeg: X01 := '0';
VARIABLE TD_DAFNeg_RSNeg : VitalTimingDataType;
VARIABLE PD_RCLK : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_RCLK : X01 := '0';
VARIABLE PD_WCLK : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_WCLK : X01 := '0';
VARIABLE PD_DAFNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_DAFNeg : X01 := '0';
-- Functionality Results Variables
VARIABLE ORF_zd : std_ulogic := 'X';
VARIABLE IRF_zd : std_ulogic := 'X';
VARIABLE AF_zd : std_ulogic := 'X';
VARIABLE HF_zd : std_ulogic := 'X';
VARIABLE Q_zd : std_ulogic_vector(17 downto 0) := (others => 'X');
-- Output Glitch Detection Variables
VARIABLE ORF_GlitchData : VitalGlitchDataType;
VARIABLE IRF_GlitchData : VitalGlitchDataType;
VARIABLE AF_GlitchData : VitalGlitchDataType;
VARIABLE HF_GlitchData : VitalGlitchDataType;
VARIABLE Q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------------------------------------------------------
-- Timing Check Section
------------------------------------------------------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => D0_ipd,
TestSignalName => "D0_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D0_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D0_WCLK );
VitalSetupHoldCheck (
TestSignal => D1_ipd,
TestSignalName => "D1_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D1_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D1_WCLK );
VitalSetupHoldCheck (
TestSignal => D2_ipd,
TestSignalName => "D2_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D2_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D2_WCLK );
VitalSetupHoldCheck (
TestSignal => D3_ipd,
TestSignalName => "D3_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D3_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D3_WCLK );
VitalSetupHoldCheck (
TestSignal => D4_ipd,
TestSignalName => "D4_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D4_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D4_WCLK );
VitalSetupHoldCheck (
TestSignal => D5_ipd,
TestSignalName => "D5_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D5_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D5_WCLK );
VitalSetupHoldCheck (
TestSignal => D6_ipd,
TestSignalName => "D6_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D6_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D6_WCLK );
VitalSetupHoldCheck (
TestSignal => D7_ipd,
TestSignalName => "D7_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D7_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D7_WCLK );
VitalSetupHoldCheck (
TestSignal => D8_ipd,
TestSignalName => "D8_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D8_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D8_WCLK );
VitalSetupHoldCheck (
TestSignal => D9_ipd,
TestSignalName => "D9_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D9_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D9_WCLK );
VitalSetupHoldCheck (
TestSignal => D10_ipd,
TestSignalName => "D10_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D10_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D10_WCLK );
VitalSetupHoldCheck (
TestSignal => D11_ipd,
TestSignalName => "D11_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D11_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D11_WCLK );
VitalSetupHoldCheck (
TestSignal => D12_ipd,
TestSignalName => "D12_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D12_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D12_WCLK );
VitalSetupHoldCheck (
TestSignal => D13_ipd,
TestSignalName => "D13_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D13_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D13_WCLK );
VitalSetupHoldCheck (
TestSignal => D14_ipd,
TestSignalName => "D14_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D14_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D14_WCLK );
VitalSetupHoldCheck (
TestSignal => D15_ipd,
TestSignalName => "D15_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D15_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D15_WCLK );
VitalSetupHoldCheck (
TestSignal => D16_ipd,
TestSignalName => "D16_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D16_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D16_WCLK );
VitalSetupHoldCheck (
TestSignal => D17_ipd,
TestSignalName => "D17_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_D0_WCLK,
SetupLow => tsetup_D0_WCLK,
HoldHigh => thold_D0_WCLK,
HoldLow => thold_D0_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D17_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D17_WCLK );
VitalSetupHoldCheck (
TestSignal => D0_ipd,
TestSignalName => "D0_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D0_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D0_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D1_ipd,
TestSignalName => "D1_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D1_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D1_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D2_ipd,
TestSignalName => "D2_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D2_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D2_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D3_ipd,
TestSignalName => "D3_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D3_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D3_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D4_ipd,
TestSignalName => "D4_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D4_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D4_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D5_ipd,
TestSignalName => "D5_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D5_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D5_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D6_ipd,
TestSignalName => "D6_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D6_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D6_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D7_ipd,
TestSignalName => "D7_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D7_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D7_DAFNeg );
VitalSetupHoldCheck (
TestSignal => D8_ipd,
TestSignalName => "D8_ipd",
RefSignal => DAFNeg_ipd,
RefSignalName => "DAFNeg_ipd",
SetupHigh => tsetup_D0_DAFNeg,
SetupLow => tsetup_D0_DAFNeg,
HoldHigh => thold_D0_DAFNeg,
HoldLow => thold_D0_DAFNeg,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_D8_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D8_DAFNeg );
VitalSetupHoldCheck (
TestSignal => WEN1_ipd,
TestSignalName => "WEN1_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_WEN1_WCLK,
HoldHigh => thold_WEN1_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_WEN1_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_WEN1_WCLK );
VitalSetupHoldCheck (
TestSignal => WEN2_ipd,
TestSignalName => "WEN2_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK_ipd",
SetupHigh => tsetup_WEN1_WCLK,
HoldHigh => thold_WEN1_WCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_WEN2_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_WEN2_WCLK );
VitalSetupHoldCheck (
TestSignal => REN1_ipd,
TestSignalName => "REN1_ipd",
RefSignal => RCLK_ipd,
RefSignalName => "RCLK",
SetupHigh => tsetup_REN1_RCLK,
HoldHigh => thold_REN1_RCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_REN1_RCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_REN1_RCLK );
VitalSetupHoldCheck (
TestSignal => REN2_ipd,
TestSignalName => "REN2_ipd",
RefSignal => RCLK_ipd,
RefSignalName => "RCLK",
SetupHigh => tsetup_REN1_RCLK,
HoldHigh => thold_REN1_RCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_REN2_RCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_REN2_RCLK );
VitalSetupHoldCheck (
TestSignal => OE_ipd,
TestSignalName => "OE_ipd",
RefSignal => RCLK_ipd,
RefSignalName => "RCLK",
SetupHigh => tsetup_OE_RCLK,
HoldHigh => thold_OE_RCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_OE_RCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_OE_RCLK );
VitalSetupHoldCheck (
TestSignal => RSNeg_ipd,
TestSignalName => "RSNeg_ipd",
RefSignal => RCLK_ipd,
RefSignalName => "RCLK",
SetupLow => tsetup_RSNeg_RCLK,
HoldLow => thold_RSNeg_RCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_RSNeg_RCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RSNeg_RCLK );
VitalSetupHoldCheck (
TestSignal => RSNeg_ipd,
TestSignalName => "RSNeg_ipd",
RefSignal => WCLK_ipd,
RefSignalName => "WCLK",
SetupLow => tsetup_RSNeg_RCLK,
HoldLow => thold_RSNeg_RCLK,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_RSNeg_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RSNeg_WCLK );
VitalSetupHoldCheck (
TestSignal => DAFNeg_ipd,
TestSignalName => "DAFNeg_ipd",
RefSignal => RSNeg_ipd,
RefSignalName => "RSNeg",
SetupLow => tsetup_DAFNeg_RSNeg,
SetupHigh => tsetup_DAFNeg_RSNeg,
HoldLow => thold_DAFNeg_RSNeg,
HoldHigh => thold_DAFNeg_RSNeg,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/fifo7881",
TimingData => TD_DAFNeg_RSNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_DAFNeg_RSNeg );
VitalPeriodPulseCheck (
TestSignal => WCLK_ipd,
TestSignalName => "WCLK_ipd",
Period => tperiod_RCLK_posedge,
PulseWidthHigh => tpw_WCLK_posedge,
PulseWidthLow => tpw_WCLK_negedge,
PeriodData => PD_WCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_WCLK,
HeaderMsg => InstancePath & "/fifo7881",
CheckEnabled => TRUE );
VitalPeriodPulseCheck (
TestSignal => RCLK_ipd,
TestSignalName => "RCLK_ipd",
Period => tperiod_RCLK_posedge,
PulseWidthHigh => tpw_RCLK_posedge,
PulseWidthLow => tpw_RCLK_negedge,
PeriodData => PD_RCLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_RCLK,
HeaderMsg => InstancePath & "/fifo7881",
CheckEnabled => TRUE );
VitalPeriodPulseCheck (
TestSignal => DAFNeg_ipd,
TestSignalName => "DAFNeg_ipd",
PulseWidthHigh => tpw_DAFNeg_posedge,
PeriodData => PD_DAFNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_DAFNeg,
HeaderMsg => InstancePath & "/fifo7881",
CheckEnabled => TRUE );
END IF; -- Timing Check Section
d := (D17_ipd, D16_ipd, D15_ipd, D14_ipd, D13_ipd, D12_ipd, D11_ipd,
D10_ipd, D9_ipd, D8_ipd, D7_ipd, D6_ipd, D5_ipd, D4_ipd, D3_ipd,
D2_ipd, D1_ipd, D0_ipd);
d := To_X01(d);
----------------------------------------------------------------------------
-- Define the AE and AF offset values
----------------------------------------------------------------------------
IF ((DAFNeg_ipd'EVENT) AND (To_X01(DAFNeg_ipd) = '0')) THEN
FOR i IN 17 DOWNTO 9 LOOP
d_temp(i) := '0' ;
END LOOP ;
ae_offset := to_nat(d_temp) ;
af_offset := to_nat(d_temp) ;
END IF ;
----------------------------------------------------------------------------
-- Program the AE and AF offsets to the default value of X = 256
----------------------------------------------------------------------------
IF ((RSNeg_ipd'EVENT) AND (To_X01(RSNeg_ipd) = '1') AND
(To_X01(DAFNeg_ipd) = '1') AND (rst = 1)) THEN
ae_offset := 256 ;
af_offset := 256 ;
END IF ;
----------------------------------------------------------------------------
-- Reset FIFO
----------------------------------------------------------------------------
IF ((RSNeg_ipd'EVENT) AND (To_X01(RSNeg_ipd) = '0')) THEN
flagstate := "X10X" ;
wordcounter := 0 ;
waddr := 0 ;
raddr := 0 ;
rst := 1 ;
rdclkcount := 0 ;
wrtclkcount := 0 ;
orflag := 0 ;
irflag := 0 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
wordcount <= wordcounter ;
END IF ;
IF ((To_X01(RSNeg_ipd) = '0') AND (RCLK_ipd'EVENT) AND
(To_X01(RCLK_ipd) = '1') AND (rst = 1)) THEN
rdclkcount := rdclkcount + 1 ;
d_temp := TO_X01(d) ;
CASE rdclkcount IS
WHEN 1 => NULL ;
WHEN 2 => NULL ;
WHEN 3 =>
flagstate := "0100" ;
ORF_zd := flagstate(0) ;
WHEN 4 => NULL ;
WHEN OTHERS => NULL ;
END CASE ;
END IF ;
IF ((To_X01(RSNeg_ipd) = '0') AND (WCLK_ipd'EVENT) AND
(To_X01(WCLK_ipd) = '1') AND (rst = 1)) THEN
wrtclkcount := wrtclkcount + 1 ;
d_temp := TO_X01(d) ;
CASE wrtclkcount IS
WHEN 1 => NULL ;
WHEN 2 =>
flagstate := "X100" ;
IRF_zd := flagstate(3) ;
WHEN 3 => NULL ;
WHEN 4 => NULL ;
WHEN OTHERS => NULL ;
END CASE ;
END IF ;
------------------------------------------------------------------------
-- Program the values for the AE and AF flags
------------------------------------------------------------------------
IF ((RSNeg_ipd'EVENT) AND (To_X01(RSNeg_ipd) = '1') AND (rst = 1) AND
(wrtclkcount >= 4) AND (rdclkcount >= 4)) THEN
ae_limit := ae_offset ;
af_limit := 1024 - af_offset ;
rst := 0 ;
wrtclkcount := 0 ;
rdclkcount := 0 ;
END IF ;
------------------------------------------------------------------------
-- Set q to high impedance
------------------------------------------------------------------------
IF (To_X01(OE_ipd) = '0') THEN
Q_zd := "ZZZZZZZZZZZZZZZZZZ" ;
ELSIF ((OE_ipd'EVENT) AND (To_X01(OE_ipd) = '1') AND (raddr = 1)) THEN
Q_zd := memory(0) ;
ELSIF ((OE_ipd'EVENT) AND (To_X01(OE_ipd) = '1') AND (raddr > 1)) THEN
Q_zd := memory(raddr - 1) ;
END IF ;
------------------------------------------------------------------------
-- Set O_R high on third rdclk after first word has been written
-- into empty memory
------------------------------------------------------------------------
IF ((RCLK_ipd'EVENT) AND (To_X01(RCLK_ipd) = '1') AND
(To_X01(RSNeg_ipd) = '1') AND (orflag = 0) AND (rst = 0)
AND (wordcounter >= 1)) THEN
rdclkcount := rdclkcount + 1 ;
d_temp := TO_X01(d) ;
CASE rdclkcount IS
WHEN 1 => NULL ;
WHEN 2 => NULL ;
WHEN 3 =>
IF (flagstate = "0101") THEN
flagstate := "1101" ;
ORF_zd := flagstate(0) ;
orflag := 1 ;
rdclkcount := 0 ;
IF (To_X01(OE_ipd) /= '0') THEN
Q_zd := memory(0) ;
END IF ;
raddr := raddr + 1 ;
wordcounter := wordcounter - 1 ;
wordcount <= wordcounter ;
ELSE
flagstate(0) := '1' ;
ORF_zd := flagstate(0) ;
orflag := 1 ;
rdclkcount := 0 ;
IF (To_X01(OE_ipd) /= '0') THEN
Q_zd := memory(0) ;
END IF ;
raddr := raddr + 1 ;
wordcounter := wordcounter - 1 ;
wordcount <= wordcounter ;
END IF ;
WHEN OTHERS => NULL ;
END CASE ;
END IF ;
------------------------------------------------------------------------
-- Set IR high on 2nd wrtclk after the 1st valid read when the fifo
-- is full
------------------------------------------------------------------------
IF ((WCLK_ipd'EVENT) AND (To_X01(WCLK_ipd) = '1') AND
(To_X01(RSNeg_ipd) = '1') AND (irflag = 0) AND (wordcounter > 2)
AND (wordcounter <= 1023 ) AND (To_X01(REN1_ipd) = '1') AND (
To_X01(REN2_ipd) = '1')) THEN
wrtclkcount := wrtclkcount + 1 ;
d_temp := TO_X01(d) ;
CASE wrtclkcount IS
WHEN 1 => NULL ;
WHEN 2 =>
flagstate := "1111" ;
IRF_zd := flagstate(3) ;
irflag := 1 ;
wrtclkcount := 0 ;
WHEN OTHERS => NULL ;
END CASE ;
END IF ;
------------------------------------------------------------------------
-- Data writes to the FIFO
------------------------------------------------------------------------
IF ((WCLK_ipd'EVENT) AND (To_X01(WCLK_ipd) = '1') AND
(To_X01(RSNeg_ipd) = '1') AND (To_X01(WEN1_ipd) = '1') AND
(To_X01(WEN2_ipd) = '1')) THEN
IF (irflag = 1) THEN
IF (waddr < 1024) THEN
memory(waddr) := To_StdULogicVector(d) ;
wordcounter := wordcounter + 1;
wordcount <= wordcounter ;
waddr := waddr + 1 ;
ELSIF (waddr = 1024) THEN
waddr := 0 ;
memory(waddr) := To_StdULogicVector(d) ;
wordcounter := wordcounter + 1 ;
wordcount <= wordcounter ;
END IF ;
END IF ;
END IF ;
------------------------------------------------------------------------
-- Data reads from the FIFO
------------------------------------------------------------------------
IF ((RCLK_ipd'EVENT) AND (To_X01(RCLK_ipd) = '1') AND
(To_X01(RSNeg_ipd) = '1') AND (To_X01(REN1_ipd) = '1') AND
(To_X01(REN2_ipd) = '1') AND (rst = 0)) THEN
IF (orflag = 1) AND (wordcount = 0) THEN
CASE flagstate IS
WHEN "1101" =>
IF (wordcounter = 0) THEN
flagstate := "0101" ;
orflag := 0 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN OTHERS => NULL ;
END CASE ;
ELSIF (orflag = 1) AND (wordcount /= 0) AND (raddr /= 0) THEN
IF (raddr < 1024) THEN
wordcounter := wordcounter - 1 ;
wordcount <= wordcounter ;
IF (To_X01(OE_ipd) /= '0') THEN
Q_zd := memory(raddr) ;
END IF ;
raddr := raddr + 1 ;
ELSIF (raddr = 1024) THEN
raddr := 0 ;
wordcounter := wordcounter - 1 ;
wordcount <= wordcounter ;
IF (To_X01(OE_ipd) /= '0') THEN
Q_zd := memory(raddr) ;
END IF ;
END IF ;
END IF ;
END IF ;
------------------------------------------------------------------------
-- Set IR high after reset
------------------------------------------------------------------------
IF ((WCLK_ipd'EVENT) AND (To_X01(WCLK_ipd) = '1') AND
(To_X01(RSNeg_ipd) = '1') AND (wordcounter = 0) AND
(rst = 0) AND (irflag = 0)) THEN
wrtclkcount := wrtclkcount + 1 ;
d_temp := TO_X01(d) ;
CASE wrtclkcount IS
WHEN 1 => NULL ;
WHEN 2 =>
flagstate := "0101" ;
IRF_zd := flagstate(3) ;
irflag := 1 ;
wrtclkcount := 0 ;
WHEN OTHERS => NULL ;
END CASE ;
END IF ;
------------------------------------------------------------------------
-- Determine the status of the FIFO and assign the flag pins
------------------------------------------------------------------------
ae_limit := ae_offset ;
af_limit := 1024 - af_offset ;
hf_limit := 512 ;
f_limit := 1024 ;
IF not Is_X(d) THEN
CASE flagstate IS
WHEN "X10X" => NULL ;
WHEN "X100" => NULL ;
WHEN "0100" => NULL ;
WHEN "0101" =>
IF ((wordcounter > ae_limit) AND (wordcounter < hf_limit)) THEN
flagstate := "0001" ;
orflag := 0 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "0001" =>
IF ((wordcounter > 0) AND (wordcounter <= ae_limit)) THEN
flagstate := "0101" ;
orflag := 0 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
IF ((wordcounter >= hf_limit) AND (wordcounter < af_limit)) THEN
flagstate := "0011" ;
orflag := 0 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "0011" =>
IF ((wordcounter > ae_limit) AND (wordcounter < hf_limit)) THEN
flagstate := "0001" ;
orflag := 0 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
IF ((wordcounter >= af_limit) AND (wordcounter < f_limit )) THEN
flagstate := "0111" ;
orflag := 0 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "0111" =>
IF ((wordcounter >= hf_limit) AND (wordcounter < af_limit)) THEN
flagstate := "0011" ;
orflag := 0 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
IF (wordcounter = f_limit ) THEN
flagstate := "0110" ;
orflag := 0 ;
irflag := 0 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "0110" => NULL ;
WHEN "1101" =>
-- IF (wordcounter = 0) THEN
-- flagstate := "0101" ;
-- orflag := 0 ;
-- irflag := 1 ;
-- ORF_zd := flagstate(0) ;
-- AF_zd := flagstate(1) ;
-- HF_zd := flagstate(2) ;
-- IRF_zd := flagstate(3) ;
-- END IF ;
IF ((wordcounter > ae_limit) AND (wordcounter < hf_limit)) THEN
flagstate := "1001" ;
orflag := 1 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "1001" =>
IF ((wordcounter > 0) AND (wordcounter <= ae_limit)) THEN
flagstate := "1101" ;
orflag := 1 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
IF ((wordcounter >= hf_limit) AND (wordcounter < af_limit)) THEN
flagstate := "1011" ;
orflag := 1 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "1011" =>
IF ((wordcounter > ae_limit) AND (wordcounter < hf_limit)) THEN
flagstate := "1001" ;
orflag := 1 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
IF ((wordcounter >= af_limit) AND (wordcounter < f_limit )) THEN
flagstate := "1111" ;
orflag := 1 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "1111" =>
IF ((wordcounter >= hf_limit) AND (wordcounter < af_limit)) THEN
flagstate := "1011" ;
orflag := 1 ;
irflag := 1 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
IF (wordcounter = f_limit ) THEN
flagstate := "1110" ;
orflag := 1 ;
irflag := 0 ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END IF ;
WHEN "1110" => NULL ;
WHEN OTHERS =>
flagstate := "XXXX" ;
ORF_zd := flagstate(0) ;
AF_zd := flagstate(1) ;
HF_zd := flagstate(2) ;
IRF_zd := flagstate(3) ;
END CASE ;
END IF ;
------------------------------------------------------------------------
-- Path Delay Section
------------------------------------------------------------------------
VitalPathDelay01 (
OutSignal => ORF,
OutSignalName => "ORF",
OutTemp => ORF_zd,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => RSNeg_ipd'LAST_EVENT,
PathDelay => (0 ns, 0 ns),
PathCondition => (RSNeg_ipd = '0') ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_ORF,
PathCondition => TRUE ) ),
GlitchData => ORF_GlitchData );
VitalPathDelay01 (
OutSignal => IRF,
OutSignalName => "IRF",
OutTemp => IRF_zd,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => RSNeg_ipd'LAST_EVENT,
PathDelay => (0 ns, 0 ns),
PathCondition => (RSNeg_ipd = '0') ),
1 => (InputChangeTime => WCLK_ipd'LAST_EVENT,
PathDelay => tpd_WCLK_IRF,
PathCondition => TRUE ) ),
GlitchData => IRF_GlitchData );
VitalPathDelay01 (
OutSignal => AF,
OutSignalName => "AF",
OutTemp => AF_zd,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => RSNeg_ipd'LAST_EVENT,
PathDelay => tpd_RSNeg_AF,
PathCondition => (RSNeg_ipd = '0') ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_AF,
PathCondition => TRUE ) ),
GlitchData => AF_GlitchData );
VitalPathDelay01 (
OutSignal => HF,
OutSignalName => "HF",
OutTemp => HF_zd,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => RSNeg_ipd'LAST_EVENT,
PathDelay => tpd_RSNeg_HF,
PathCondition => (RSNeg_ipd = '0') ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_HF,
PathCondition => TRUE ) ),
GlitchData => HF_GlitchData );
VitalPathDelay01Z (
OutSignal => Q17,
OutSignalName => "Q17",
OutTemp => Q_zd(17),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q16,
OutSignalName => "Q16",
OutTemp => Q_zd(16),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q15,
OutSignalName => "Q15",
OutTemp => Q_zd(15),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q14,
OutSignalName => "Q14",
OutTemp => Q_zd(14),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q13,
OutSignalName => "Q13",
OutTemp => Q_zd(13),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q12,
OutSignalName => "Q12",
OutTemp => Q_zd(12),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q11,
OutSignalName => "Q11",
OutTemp => Q_zd(11),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q10,
OutSignalName => "Q10",
OutTemp => Q_zd(10),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q9,
OutSignalName => "Q9",
OutTemp => Q_zd(9),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q8,
OutSignalName => "Q8",
OutTemp => Q_zd(8),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q7,
OutSignalName => "Q7",
OutTemp => Q_zd(7),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q6,
OutSignalName => "Q6",
OutTemp => Q_zd(6),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q5,
OutSignalName => "Q5",
OutTemp => Q_zd(5),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q4,
OutSignalName => "Q4",
OutTemp => Q_zd(4),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q3,
OutSignalName => "Q3",
OutTemp => Q_zd(3),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q2,
OutSignalName => "Q2",
OutTemp => Q_zd(2),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q1,
OutSignalName => "Q1",
OutTemp => Q_zd(1),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
VitalPathDelay01Z (
OutSignal => Q0,
OutSignalName => "Q0",
OutTemp => Q_zd(0),
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => OE_ipd'LAST_EVENT,
PathDelay => tpd_OE_Q0,
PathCondition => TRUE ),
1 => (InputChangeTime => RCLK_ipd'LAST_EVENT,
PathDelay => tpd_RCLK_Q0,
PathCondition => TRUE ) ),
GlitchData => Q_GlitchData );
END PROCESS;
END vhdl_behavioral;