-- three levels of timing modeling for 8-bit REGister

entity REGISTRE is
port(di: in BIT_VECTOR(1 to 8); strb: in BIT;
     ds1,nds2: in BIT; do: out BIT_VECTOR(1 to 8));
end REGISTRE;

-- first implementation
architecture DELTA_DELAY_TIMING of REGISTRE is
signal reg: BIT_VECTOR(1 to 8);
begin
  DELTA:process(strb,ds1,nds2)
  begin
    if strb='1' and not strb'stable then
      reg <= di;
      if ds1='1' and nds2='0' then
	do <= di;
      else
	do <= "11111111";
      end if;
    elsif not ds1'stable or not nds2'stable then
      if ds1='1' and nds2='0' then
	do <= reg;
      else
	do <= "11111111";
      end if;
    end if;
  end process DELTA;
end DELTA_DELAY_TIMING;

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