-- three levels of timing modeling for 8-bit REGister

entity REGISTRE is
port(di: in BIT_VECTOR(1 to 8); strb: in BIT;
     ds1,nds2: in BIT; do: out BIT_VECTOR(1 to 8));
end REGISTRE;

-- first implementation
architecture DELTA_DELAY_TIMING of REGISTRE is
signal reg: BIT_VECTOR(1 to 8);
begin
  DELTA:process(strb,ds1,nds2)
  begin
    if strb='1' and not strb'stable then
      reg <= di;
      if ds1='1' and nds2='0' then
	do <= di;
      else
	do <= "11111111";
      end if;
    elsif not ds1'stable or not nds2'stable then
      if ds1='1' and nds2='0' then
	do <= reg;
      else
	do <= "11111111";
      end if;
    end if;
  end process DELTA;
end DELTA_DELAY_TIMING;


-- second implementation
architecture SIMPLE_IO_TIMING of REGISTRE is
signal reg: BIT_VECTOR(1 to 8);
constant strb_del:TIME:=40ns;
constant odel:TIME:=60ns;
constant en_del:TIME:=20ns;
begin
  SIMPLE:process(strb,ds1,nds2)
  begin
    if strb='1' and not strb'stable then
      reg <= di after strb_del ;
      if ds1='1' and nds2='0' then
	do <= di after strb_del+odel;
      else
	do <= "11111111" after strb_del+odel;
      end if;
    elsif not ds1'stable or not nds2'stable then
      if ds1='1' and nds2='0' then
	do <= reg after en_del+odel;
      else
	do <= "11111111" after en_del+odel;
      end if;
    end if;
  end process SIMPLE;
end SIMPLE_IO_TIMING; 

-- third implementation
architecture NODAL of REGISTRE is
signal reg: BIT_VECTOR(1 to 8);
signal enbld: BIT;
constant strb_del:TIME:=40ns;
constant odel:TIME:=60ns;
constant en_del:TIME:=20ns;
  begin
  A:process(strb)
    begin
    if strb='1' then
      reg <= di after strb_del;
      end if;
    end process A;
  B:process(ds1,nds2)
    begin
    enbld <= ds1 and not nds2 after en_del;
    end process B;
  C:process(reg,enbld)
    begin
    if enbld='1' then
      do <= reg after odel;
    else
      do <= "11111111" after odel;
    end if;
    end process C;
end NODAL;

-- fourth implementation : data-flow
architecture DATA_FLOW of REGISTRE is
constant strb_del:TIME:=40ns;
constant odel:TIME:=60ns;
constant en_del:TIME:=20ns;
begin
  B1:block(strb='1' and not strb'stable)
  signal reg: BIT_VECTOR(1 to 8);
  signal enbld: BIT;
  begin
    reg <= guarded di after strb_del; -- process A
    enbld <= ds1 and not nds2 after en_del; -- process B
    do <= reg after odel when enbld='1'
	  else "11111111" after odel; -- process C
  end block B1;
end DATA_FLOW;

-- end of  REGISTRE examples


entity vREG is
end vREG;

architecture SIMPLE of vREG is
signal d: BIT_VECTOR(1 to 8);
signal s,pe,ne:BIT;
component REGISTRE 
port(di: in BIT_VECTOR(1 to 8); strb: in BIT;
     ds1,nds2: in BIT; do: out BIT_VECTOR(1 to 8));
end component ;
for iR: REGISTRE
  use entity work.REGISTRE(NODAL);

begin
  iR: REGISTRE
  port map(d,s,pe,ne,open);
process
  begin
  d<="10101010","11110000" after 30ns, "00001111" after 70ns, 
     "10110100" after 125ns, "01000111" after 180ns; 
  s<='1' after 20ns,'0' after 50ns, '1' after 80ns;
  ne<='1' after 50ns, '0' after 80ns,'1' after 100ns ;
  pe<='1' after 10ns, '0' after 120ns,'1' after 150ns;
  wait;
end process;
end SIMPLE;


<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br />&nbsp;</div>