----------------------------------------------------------------------------------
--  Antonio E COSTA						Jerome CAZIN	--
--				SEII3 - Decembre 96				--
--										--
--	Entite FIFO_out : Buffer de sortie qui ont une capacite totale de 	--
--		    	  4 cellules, soit 4*7=28 mots de 64 bits		--
----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
--				FIFO_sortie				  	--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FIFO_out is

   port(   RAZ		: in std_logic;
	   CLK		: in std_logic;
	   WRITE	: in std_logic;
	   DI		: in std_logic_vector(63 downto 0);
	   READ		: in std_logic;
	   DO		: out std_logic_vector(63 downto 0);
	   RDEN		: out std_logic;
	   WREN		: out std_logic
	  
	);
 end FIFO_out;
 
 ---------------------------------------------------------------------------------
 --			DEFINITION DU BUFFER FIFO_out		     		--
 ---------------------------------------------------------------------------------
 architecture FIFO_out_ARC of FIFO_out is
  type TYPE_BUFFER is array (0 to 27) 
		      of std_logic_vector(63 downto 0);
  subtype NATURALptr	is NATURAL range 0 to 27;
  type TYPE_ETAT is (Repos,Lecture,Ecriture);
		      
  signal BUF		: TYPE_BUFFER; --compass mem_style BUF RAM
  
  
 begin
  
  process (CLK,RAZ)    	
  variable P_I,P_O	: NATURALptr;
  variable PLEIN,VIDE	: std_logic; 
  variable ETAT		: TYPE_ETAT;
  variable ATTENTE	: BOOLEAN;
  
    begin
    -- commande RAZ
    if (RAZ='1') then
    	P_I:=0;
	P_O:=0;
	PLEIN:='0';
	VIDE:='1';
	RDEN <= '0';
	WREN <= '0';
	DO <= (others =>'0');
	ETAT:=Repos;
	ATTENTE:=FALSE;
	
    elsif RISING_EDGE(CLK) then
    case ETAT is
      when Repos =>
	RDEN <='L';
	WREN <='L';
	DO  <= (others=>'Z');

	if WRITE='1' and PLEIN/='1' then 
		WREN<='1';
		ETAT:=Ecriture;
	end if;
	
    	if READ='1' and VIDE/='1' and not (WRITE='1' and PLEIN/='1') then 
    		ETAT:=Lecture; 
    		RDEN <='1';
    		DO<=BUF(P_O) ;
    	end if;

      when Ecriture =>
	if ATTENTE=FALSE then 
		WREN <= '1';
		BUF(P_I)<=DI;
		if P_I = 27 then P_I:=0;
		else P_I:=P_I+1;
		end if;
		VIDE:='0';
		if P_I=P_O then 
			PLEIN:='1'; -- memoire saturee
		end if;
	end if;
	if WRITE = '0' then ETAT:=Repos;ATTENTE:=FALSE;
	else ATTENTE:=TRUE;
	end if;

       when Lecture =>
	if ATTENTE=FALSE then 
		if P_O = 27 then P_O:=0;
		else P_O:=P_O+1;end if;
		PLEIN:='0';
		if P_I=P_O then
			VIDE:='1'; -- memoire vide
		end if;
	end if;
	if READ = '0' then ETAT:=Repos; ATTENTE:=FALSE;
	else ATTENTE:=TRUE;
	end if;

	when others => ETAT:=Repos;
    end case;
    end if;
 end process;
 end FIFO_out_ARC;

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