---------------------------------------------------------------------------------- -- Antonio E COSTA Jerome CAZIN -- -- SEII3 - Decembre 96 -- -- -- -- Entite Controle entree, entite qui gere l'arrivee des cellules -- -- -- ---------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------- -- Contrôle entrées -- -------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity CTRL_ENTREES is port( RESETB :in std_logic; CLK :in std_logic; RDEN :in std_logic; ENTREE_DONNEE:in std_logic_vector (63 downto 0); SORTIE_DONNEE:out std_logic_vector(63 downto 0); READ :out std_logic_vector(3 downto 0); VCI :out std_logic_vector(15 downto 0); prete :out std_logic; consom :in std_logic ); end CTRL_ENTREES; ---------------------------------------------------------------------- -- DEFINITION DE CONTROLE ENTREES -- ---------------------------------------------------------------------- architecture CTRL_ENTREES_ARC of CTRL_ENTREES is type TYPE_ETAT is (Lect_entete,attente,boucle,next_word); constant TIMEMAX : NATURAL :=2; subtype NATURAL3 is NATURAL range 0 to 2; subtype NATURAL16 is NATURAL range 0 to 15; subtype NATURAL7 is NATURAL range 0 to 6; begin process(CLK,RESETB) variable ETAT : TYPE_ETAT; variable timeout : NATURAL3; variable N_WORD : NATURAL7; variable N_ENTREE : NATURAL16; begin if RESETB = '1' then ETAT:=Lect_entete; N_ENTREE :=0; prete<='0'; READ <= (others =>'0'); VCI <= (others =>'0'); SORTIE_DONNEE <= (others => '0'); ETAT:= Lect_entete; elsif RISING_EDGE(clk) then case ETAT is when Lect_entete => READ(N_ENTREE)<='1'; N_WORD := 0; if RDEN='1' and consom = '0' then TIMEOUT:=0; ETAT:=boucle; VCI(15 downto 0) <=ENTREE_DONNEE (27 downto 12); SORTIE_DONNEE <= ENTREE_DONNEE; prete <= '1'; else ETAT:=Attente; end if; when Attente => if RDEN='L' or consom ='1' then if TIMEOUT/=TIMEMAX then TIMEOUT:=TIMEOUT+1; elsif N_entree=3 then N_entree:=0; READ <= (others => '0'); else N_ENTREE:=N_ENTREE+1; TIMEOUT:=0; READ <= (others => '0'); end if; ETAT:= Lect_entete; elsif RDEN='1' and consom = '0' then ETAT:=boucle; TIMEOUT:=0; VCI(15 downto 0) <=ENTREE_DONNEE (27 downto 12); SORTIE_DONNEE <= ENTREE_DONNEE; prete <= '1'; end if; when boucle => READ(N_ENTREE)<='0'; prete <='0'; if N_WORD=6 and RDEN = 'L' then if N_ENTREE=3 then N_ENTREE:=0; else N_ENTREE:=N_ENTREE+1;end if; ETAT:=lect_entete; elsif RDEN = 'L' then N_WORD:=N_WORD + 1; ETAT:=next_word; end if; when next_word => READ(N_ENTREE)<='1'; if RDEN = '1' and consom = '0' then ETAT:=boucle; SORTIE_DONNEE<=ENTREE_DONNEE; prete <= '1'; end if; when others => ETAT:=Lect_entete; end case; end if; end process; end CTRL_ENTREES_ARC;