----------------------------------------------------------------------------------
--  Antonio E COSTA						Jerome CAZIN	--
--				SEII3 - Decembre 96				--
--										--
--	Instanciation des composants qui composent le coeur du commutateur	--
--		       								--
----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
--				FIFO						--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FIFO is
   generic(NB_BITS	:INTEGER;
	   NB_WORDS	:INTEGER
	  );

   port(   RAZ		: in std_logic;
	   CLK		: in std_logic;
	   WRITE	: in std_logic;
	   DI		: in std_logic_vector(NB_BITS downto 1);
	   READ		: in std_logic;
	   DO		: out std_logic_vector(NB_BITS downto 1);
	   RDEN		: out std_logic;
	   WREN		: out std_logic
	  
	);
 end FIFO;




----------------------------------------------------------------------------------
--				Contrôle entrées				--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity CTRL_ENTREES is
   port(   RESETB	:in std_logic;
	   CLK		:in std_logic;
	   RDEN		:in std_logic;
	   ENTREE_DONNEE:in std_logic_vector (63 downto 0);
	   SORTIE_DONNEE:out std_logic_vector(63 downto 0);
	   READ		:out std_logic_vector(15 downto 0);
	   VCI		:out std_logic_vector(15 downto 0);
	   prete	:out std_logic;
	   consom	:in std_logic
	  
	);
end CTRL_ENTREES;

----------------------------------------------------------------------------------
--				Contrôle Sorties			  	--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity CTRL_SORTIES is
   port(  RESETB	:in std_logic;
	  CLK		:in std_logic;
	  SORTIE_DONNEE :in std_logic_vector(63 downto 0);
	  WREN		:in std_logic;
	  VCI		:in std_logic_vector(15 downto 0);
	  BUS_SORTIE	:out std_logic_vector (63 downto 0);
	  consom	:out std_logic;
	  WRITE		:out std_logic_vector(16 downto 1);
	  prete		:in std_logic
	);

end CTRL_SORTIES;


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