---------------------------------------------------------------------------------- -- Antonio E COSTA Jerome CAZIN -- -- SEII3 - Decembre 96 -- -- -- -- Description de l'architecure des composants au niveau RTL -- -- d -- ---------------------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- -- -- -- DEFINITION DU CORPS DES COMPOSANTS -- -- -- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- -- DEFINITION DU BUFFER FIFO -- ---------------------------------------------------------------------- architecture FIFO_ARC of FIFO is begin process (CLK,RAZ) type TYPE_BUFFER is array (0 to NB_WORDS-1) of std_logic_vector(NB_BITS-1 downto 0); subtype MY_NATURAL is NATURAL range 0 to NB_WORDS-1; type TYPE_ETAT is (Repos,Lecture,Ecriture); -- declaraion des variables variable ETAT : TYPE_ETAT:=Repos; variable BUF : TYPE_BUFFER; variable P_I,P_O : MY_NATURAL :=0; -- pointeurs de pile variable PLEIN : std_logic:='0'; -- indicateur de memoire saturee variable VIDE : std_logic:='1'; -- indicateur de memoire vide variable ATTENTE : BOOLEAN:=FALSE; begin -- commande RAZ if RAZ='1' then P_I:=0; P_O:=0; PLEIN:='0'; VIDE :='1'; RDEN <= '0'; WREN <= '0'; DO <= (others => 'Z'); elsif RISING_EDGE(CLK) then case ETAT is when Repos => RDEN <='L'; WREN <='L'; DO<=(others =>'Z'); if WRITE='1' and PLEIN/='1' then WREN<='1';ETAT:=Ecriture; end if; if READ='1' and VIDE/='1' and ETAT /=Ecriture then ETAT:=Lecture; RDEN <='1';DO<=BUF(P_O) ; end if; when Ecriture => if ATTENTE=FALSE then WREN <= '1'; BUF(P_I):=DI; if P_I = NB_WORDS-1 then P_I:=0; else P_I:=P_I+1;end if; VIDE:='0'; if P_I=P_O then PLEIN:='1'; -- memoire saturee end if; end if; if WRITE = '0' then ETAT:=Repos;ATTENTE:=FALSE; else ATTENTE:=TRUE; end if; when Lecture => if ATTENTE=FALSE then if P_O = NB_WORDS-1 then P_O:=0; else P_O:=P_O+1;end if; PLEIN:='0'; if P_I=P_O then VIDE:='1'; -- memoire vide end if; end if; if READ = '0' then ETAT:=Repos; ATTENTE:=FALSE; else ATTENTE:=TRUE; end if; when others => ETAT:=Repos; end case; end if; end process; end FIFO_ARC; ---------------------------------------------------------------------- -- DEFINITION DE CONTROLE ENTREES -- ---------------------------------------------------------------------- architecture CTRL_ENTREES_ARC of CTRL_ENTREES is type TYPE_ETAT is (Lect_entete,attente,boucle,next_word); signal ETAT : TYPE_ETAT:=Lect_entete; constant TIMEMAX :integer :=2; signal timeout : NATURAL; begin process(CLK,RESETB) subtype NATURAL16 is NATURAL range 0 to 15; subtype NATURAL7 is NATURAL range 0 to 6; variable N_WORD : NATURAL7; variable N_ENTREE : NATURAL16; begin if RESETB = '1' then ETAT<=Lect_entete; N_ENTREE :=0; prete<='0'; READ <= (others =>'0'); VCI <= (others =>'0'); SORTIE_DONNEE <= (others => '0'); elsif RISING_EDGE(clk) then case ETAT is when Lect_entete => READ(N_ENTREE)<='1'; N_WORD := 0; if RDEN='1' and consom = '0' then TIMEOUT<=0; ETAT<=boucle; VCI(15 downto 0) <=ENTREE_DONNEE (27 downto 12); SORTIE_DONNEE <= ENTREE_DONNEE; prete <= '1'; else ETAT<=Attente; end if; when Attente => if RDEN='L' or consom ='1' then if TIMEOUT/=TIMEMAX then TIMEOUT<=TIMEOUT+1; elsif N_entree=15 then N_entree:=0; READ <= (others => '0'); else N_ENTREE:=N_ENTREE+1; TIMEOUT<=0; READ <= (others => '0'); end if; ETAT<= Lect_entete; elsif RDEN='1' and consom = '0' then ETAT<=boucle; TIMEOUT<=0; VCI(15 downto 0) <=ENTREE_DONNEE (27 downto 12); SORTIE_DONNEE <= ENTREE_DONNEE; prete <= '1'; end if; when boucle => READ(N_ENTREE)<='0'; prete <='0'; if N_WORD=6 and RDEN = 'L' then if N_ENTREE=15 then N_ENTREE:=0; else N_ENTREE:=N_ENTREE+1;end if; ETAT<=lect_entete; elsif RDEN = 'L' then N_WORD:=N_WORD + 1; ETAT<=next_word; end if; when next_word => READ(N_ENTREE)<='1'; if RDEN = '1' and consom = '0' then ETAT<=boucle; SORTIE_DONNEE<=ENTREE_DONNEE; prete <= '1'; end if; when others => ETAT<=Lect_entete; end case; end if; end process; end CTRL_ENTREES_ARC; -------------------------------------------------------------------------------------------- -- Definition de Contrôle Sorties -- -------------------------------------------------------------------------------------------- architecture CTRL_SORTIES_ARC of CTRL_SORTIES is type TYPE_ETAT is (Repos,ATTENTE,Ecriture); signal ETAT :TYPE_ETAT; begin process (CLK,RESETB) variable VCIT :std_logic_vector (15 downto 0); begin if RESETB = '1' then ETAT<=Repos; VCIT := (others =>'0'); consom <='0'; WRITE <= (others =>'0'); BUS_SORTIE <= (others => '0'); elsif RISING_EDGE(CLK) then case ETAT is when Repos => if prete = '1' then ETAT<=ATTENTE; VCIT:=VCI; BUS_SORTIE<=SORTIE_DONNEE; consom <='1'; end if; when ATTENTE=> case VCIT (4 downto 0) is when "00001"=> WRITE(1) <='1'; when "00010"=> WRITE(2) <='1'; when "00011"=> WRITE(3) <='1'; when "00100"=> WRITE(4) <='1'; when "00101"=> WRITE(5) <='1'; when "00110"=> WRITE(6) <='1'; when "00111"=> WRITE(7) <='1'; when "01000"=> WRITE(8) <='1'; when "01001"=> WRITE(9) <='1'; when "01010"=> WRITE(10) <='1'; when "01011"=> WRITE(11) <='1'; when "01100"=> WRITE(12) <='1'; when "01101"=> WRITE(13) <='1'; when "01110"=> WRITE(14) <='1'; when "01111"=> WRITE(15) <='1'; when "10000"=> WRITE(16) <='1'; when others => ETAT<=Ecriture; end case; if WREN = '1' and PRETE='0' then ETAT<=Ecriture; consom<='0'; end if; when Ecriture => WRITE<=(others => '0'); if PRETE='1' and WREN = 'L' then ETAT<=ATTENTE; VCIT:=VCI; BUS_SORTIE<=SORTIE_DONNEE; consom<='1'; end if; when others => ETAT<=Repos; end case; end if; end process; end CTRL_SORTIES_ARC;