library syst;
use syst.TSL.all;use syst.SYS.all;

entity RAMR is
generic(decdel,wsdel,ddel,rdel,disdel: POSITIVE);
port(data:inout WORD;address:in ADDR;read,write,cs:BIT);
end RAMR;

architecture REALISTIC of RAMR is
type MEMORY is array(0 to 31) of WORD;
signal mem: MEMORY;
signal ddata:WORD;
signal daddress:ADDR;
signal wsel:BIT;
begin
  daddress<= address after decdel*1ns;
  wsel<= write and cs after wsdel*1ns;
  ddata<= data after ddel*1ns;
READ_PROC: process(daddress,cs,read)
  begin
    if cs='1' then
      if read='1' then
	data <= mem(INTVAL(daddress)) after rdel*1ns;
      end if;
    else
      if not cs'stable then
	data <= "ZZZZZZZZ" after disdel*1ns;
      end if;
    end if;
  end process READ_PROC;

WRITE_PROC: process(wsel,ddata,daddress)
  begin
    if wsel='1' then
      mem(INTVAL(daddress))<=ddata;
    end if;
  end process WRITE_PROC;
end REALISTIC;


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