library syst;
use syst.TSL.all; use syst.SYS.all;
entity RAM is
generic(rdel,disdel: POSITIVE);
port(data:inout WORD;address:in ADDR;read,write,cs:BIT);
end RAM;

architecture SIMPLE of RAM is
begin
  READ_WRITE:process(cs,read,write)
  type MEMORY is array(0 to 31) of WORD;
  variable mem: MEMORY;
  begin
    if cs='1' then
      if not read'stable then
	if read='1' then
	  data <= mem(INTVAL(address)) after rdel*1ns;
        else
	  data <= "ZZZZZZZZ" after disdel*1ns;
	end if;
      elsif write='1' and not write'stable then
	mem(INTVAL(address)):= data;
      end if;
      else
        data <= "ZZZZZZZZ" after disdel*1ns;
    end if;
  end process READ_WRITE;
end SIMPLE;


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