library lgates;
use lgates.all;
architecture STRUCTURE of ALU_stage is
  signal notc1,notb1,notm:BIT;
  signal z1,z2,z3,z4,z5,z6,z7,z8,z9,z10:BIT;
  component AND2
    port(i1,i2:in BIT;o1:out BIT);
  end component;
  component AND3
    port(i1,i2,i3:in BIT;o1:out BIT);
  end component;
  component NAND2
    port(i1,i2:in BIT;o1:out BIT);
  end component;
  component NOR2
    port(i1,i2:in BIT;o1:out BIT);
  end component;
  component NOR3
    port(i1,i2,i3:in BIT;o1:out BIT);
  end component;
  component INVERTER
    port(i1:in BIT;o1:out BIT);
  end component;
  component XOR2
    port(i1,i2:in BIT;o1:out BIT);
  end component;
for all:AND3 use entity lgates.AND3(AND3);
for all:AND2 use entity lgates.AND2(AND2);
for all:NOR2 use entity lgates.NOR2(NOR2);
for all:NOR3 use entity lgates.NOR3(NOR3);
for all:XOR2 use entity lgates.XOR2(XOR2);
for all:NAND2 use entity lgates.NAND2(NAND2);
for all:INVERTER use entity lgates.INVERTER(INVERTER);
begin
U0:INVERTER port map(b1,notb1);
U1:AND3 port map(b1,s3,a1,z1);
U2:AND3 port map(a1,s2,notb1,z2);
U3:AND2 port map(notb1,s1,z3);
U4:AND2 port map(s0,b1,z4);
U5:NOR2 port map(z1,z2,z5);
U6:NOR3 port map(z3,z4,a1,z6);
U7:INVERTER port map(m,notm);
U8:XOR2 port map(z5,z6,z7);
U9:AND3 port map(notc1,z5,notm,z8);
U10:AND2 port map(z6,notm,z9);
U11:NAND2 port map(notc1,notm,z10);
U12:NOR2 port map(z8,z9,c2);
U13:XOR2 port map(z7,z10,f1);
U14:INVERTER port map(c1,notc1);
end STRUCTURE;


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