architecture LOGIC of ALU_stage is
begin
c2<=
    ((not c1) and((b1 and s3 and a1) nor (a1 and s2 and(not b1)))
    and (not m))
    nor ((not(((not b1) and s1) or (s0 and b1) or a1))
    and (not m)) after 20ns;
f1<=
    (((b1 and s3 and a1) nor (a1 and s2 and (not b1)))
    xor (not(((not b1) and s1) or (s0 and b1) or a1)))
    xor ((not c1) nand (not m)) after 20ns;
end LOGIC;


<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br />&nbsp;</div>