architecture FLOW of ALU_stage is
  signal notc1,notb1,notm:BIT;
  signal z1,z2,z3,z4,z5,z6,z7,z8,z9,z10:BIT;
  constant delay:TIME:=5ns;
begin
U0:notb1<= not b1 after delay;
U1:z1 <= b1 and s3 and a1 after delay;
U2:z2 <= a1 and s2 and notb1 after delay;
U3:z3 <= notb1 and s1 after delay;
U4:z4 <= s0 and b1 after delay;
U5:z5 <= z1 nor z2 after delay;
U6:z6 <= not(z3 or z4 or a1) after delay;
U7:notm <= not m after delay;
U8:z7 <= z5 xor z6 after delay;
U9:z8 <= notc1 and z5 and notm after delay;
U10:z9 <= z6 and notm after delay;
U11: c2 <= z8 nor z9 after delay;
U12: z10 <= notc1 nand notm after delay;
U13: f1 <= z7 xor z10 after delay;
U14: notc1 <= not c1 after delay;
end FLOW;


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