


                 VHDL Static Error Test Objectives



INTRODUCTION

This document outlines the test objectives and corresponding test file
names for those tests comprising the "static error" portion of the test
suite.  These tests (327 total) were provided by Vantage Analysis Systems, 
Inc., and are intended to verify that errors which typically can be detected
by the VHDL Analyzer (Compiler) are caught.

The following is organized by sections as they appear in the IEEE Standard
VHDL Language Reference Manual 1076-1987; note that sections for which no 
tests exist have been omitted.  Objective entries within each section
consist of an objective description and a list of the static error test
files which address the objective.

To better relate test objectives to the LRM, Vantage has chosen to use the
file naming convention "rgrce_CC_PPP_FF_LL_TTT.vhd" where

    o CC is a two digit LRM chapter number;
    o PPP is a three digit LRM paragraph number;
    o FF is the first two letters of the significant sentence;
    o LL is the last two letters of the significant sentence; and
    o TTT is a three digit test number.

For example, for paragraph 4 in chapter 2 with the significant sentence
"A subprogram declaration declares ... reserved word.", the file would
be "rgrce_02_004_as_rd_001.vhd".



TEST OBJECTIVES

2.1 Subprogram Declarations

    Objective: Verify that improper subprogram declarations get detected.
    Test(s)  : rgrce_02_004_as_rd_001.vhd
     
    Objective: Test syntax of subprogram declarations
    Test(s)  : rgrce_02_005_ap_er_001.vhd
               rgrce_02_005_ap_er_002.vhd
     
    Objective: Verify that it is illegal for a procedure designator to
               be anything but an identifier.
    Test(s)  : rgrce_02_005_ap_ol_000.vhd
     
    Objective: Test that the string representing an overloaded operator
               may not contain blanks.
    Test(s)  : rgrce_02_005_th_nt_001.vhd
     
    Objective: Test syntax of subprogram declarations
    Test(s)  : rgrce_02_005_th_nt_002.vhd
     

2.1.1 Formal Parameters

    Objective: Test formal parameters usage
    Test(s)  : rgrce_02_009_if_ed_001.vhd
               rgrce_02_009_if_ed_002.vhd
               rgrce_02_009_th_ed_001.vhd
     
    Objective: Test syntax for formal parameters.
    Test(s)  : rgrce_02_010_th_al_001.vhd
               rgrce_02_010_th_ly_001.vhd
               rgrce_02_011_th_le_001.vhd
     
    Objective: Test that a SIGNAL formal in a subprogram may not be 
               associated with a CONSTANT actual.
    Test(s)  : rgrce_02_011_in_al_001.vhd
     
    Objective: Test that a SIGNAL formal in a subprogram may not be 
               associated with a VARIABLE actual.
    Test(s)  : rgrce_02_011_in_al_002.vhd
     

2.1.1.2 Signal Parameters

    Objective: Check that reading 'stable, 'quiet, and 'delayed for an
               IN signal in a subprogram generates an error
    Test(s)  : rgrce_02_021_it_am_001.vhd
     
    Objective: Check that reading 'stable, 'quiet, and 'delayed for an
               INOUT signal in a subprogram generates an error
    Test(s)  : rgrce_02_021_it_am_002.vhd
     
    Objective: Check that reading 'stable, 'quiet, and 'delayed for an
               OUT signal in a subprogram generates an error
    Test(s)  : rgrce_02_021_it_am_003.vhd
     

2.2 Subprogram Bodies

    Objective: For a subprogram declared in an entity, there must be a
               corresponding body defined in the architecture.
    Test(s)  : rgrce_02_028_fo_dy_001.vhd
     
    Objective: For a subprogram declared in an architecture, there must
               be a corresponding body defined in that architecture.
    Test(s)  : rgrce_02_028_fo_dy_002.vhd
     
    Objective: For a subprogram declared in a package decl, there must
               be a corresponding body defined in the package body.
    Test(s)  : rgrce_02_028_fo_dy_003.vhd
     
    Objective: For a subprogram declared in a package body, there must
               be a corresponding body defined in that package body.
    Test(s)  : rgrce_02_028_fo_dy_004.vhd
     
    Objective: A subprogram body specification must conform to the
               same subprogram declaration
    Test(s)  : rgrce_02_028_if_on_001.vhd
               rgrce_02_028_if_on_002.vhd
     
    Objective: Check subprogram identifier usage in the end statement
    Test(s)  : rgrce_02_029_if_am_001.vhd
               
    Objective: Check declaration of signals and variables referenced within
               a function or a procedure
    Test(s)  : rgrce_02_033_if_on_001.vhd
     

3.1 Scalar Types

    Objective: Test syntax of type declaration create an error
    Test(s)  : rgrce_03_010_sc_ue_001.vhd
               rgrce_03_010_sc_ue_002.vhd
               rgrce_03_010_sc_ue_003.vhd
     
    Objective: An assignment of a value which is not in the range must
               generate an error
    Test(s)  : rgrce_03_012_th_ge_002.vhd
               rgrce_03_012_th_ge_003.vhd
     
    Objective: If L > R the range is a null range
    Test(s)  : rgrce_03_012_th_pe_001.vhd
        
    Objective: Test subtype definition  -- create an error
    Test(s)  : rgrce_03_014_if_pe_001.vhd
        

3.1.1 Enumeration Types

    Objective: Assignment of a literal which is not a member of the
               enumeration is an error
    Test(s)  : rgrce_03_018_th_al_001.vhd
     
    Objective: Make sure that a literal is not confused with a symbol
               in the enumeration
    Test(s)  : rgrce_03_020_ea_ue_001.vhd

     
3.1.1.1 Predefined Enumeration Types

    Objective: Test predefined severity_level type with non-existent value
    Test(s)  : rgrce_03_023_th_el_001.vhd

        
3.1.2 Integer Types

    Objective: Test integer type bounds generate an error using real for 
               one bound
    Test(s)  : rgrce_03_030_ea_ed_001.vhd
     
    Objective: Test integer literal type by generating an error
    Test(s)  : rgrce_03_031_in_pe_001.vhd

        
3.1.2.1 Predefined Integer Types

    Objective: Test that a definition of an integer subtype outside the 
               range creates an error
    Test(s)  : rgrce_03_035_th_ge_001.vhd

     
3.1.3 Physical Types

    Objective: Two bounds must have integer type create an error
    Test(s)  : rgrce_03_039_ea_ed_001.vhd
     
    Objective: Test a invalid definition of secondary units definition
    Test(s)  : rgrce_03_040_ea_ar_001.vhd
               rgrce_03_041_th_al_001.vhd
     
    Objective: If 1 is not in the range specified then the name of the unit 
               without a number is not a valid secondary units definition
    Test(s)  : rgrce_03_046_th_pe_001.vhd

     
3.2.1 Array Types

    Objective: Test array types
    Test(s)  : rgrce_03_062_an_nt_001.vhd
               rgrce_03_062_an_nt_002.vhd
               rgrce_03_062_an_nt_003.vhd
               rgrce_03_062_an_nt_004.vhd


3.2.1.1 Index Constraints and Discrete Ranges

    Objective: Test index constraints typing rules
    Test(s)  : rgrce_03_072_fo_me_001.vhd
               rgrce_03_072_fo_me_002.vhd
        
    Objective: Test index constraints usage
    Test(s)  : rgrce_03_073_if_ex_001.vhd
               rgrce_03_073_if_ex_002.vhd
        
    Objective: Index range usage
    Test(s)  : rgrce_03_076_fo_pe_001.vhd
        

3.2.1.2 Predefined Array Types

    Objective: Predefined array type string
    Test(s)  : rgrce_03_091_th_ve_001.vhd
        
    Objective: Predefined array type bit_vector
    Test(s)  : rgrce_03_092_th_al_001.vhd

        
3.2.2 Record Types

    Objective: Record type definition, non-unique element identifiers
    Test(s)  : rgrce_03_094_th_ct_001.vhd
        
    Objective: Record type definition, element name used within the record
               as a definition for another element
    Test(s)  : rgrce_03_094_th_nt_001.vhd

     
4.2 Subtype Declarations

    Objective: Check illegal syntax for a subtype declaration.
    Test(s)  : rgrce_04_011_as_pe_000.vhd
               rgrce_04_011_as_pe_001.vhd
     
    Objective: Verify that two subtypes which have different base types
               cannot be compared.
    Test(s)  : rgrce_04_012_th_rk_001.vhd
     
    Objective: Verify that subtype indications for access and file types
               may not contain a resolution function.
    Test(s)  : rgrce_04_017_as_on_000.vhd
     

4.3.2 File Declarations

    Objective: Verify that it is illegal to assign to a file object.
    Test(s)  : rgrce_04_059_in_ed_000.vhd
     
    Objective: Test illegal syntax for file declarations.
    Test(s)  : rgrce_04_059_in_ed_001.vhd
               rgrce_04_059_in_ed_002.vhd
     
    Objective: Test that the subtype indication of a file declaration
               must define a file subtype.
    Test(s)  : rgrce_04_060_th_pe_000.vhd
     
    Objective: Test that all other modes other than 'in' and 'out' are 
               illegal for external file associations.
    Test(s)  : rgrce_04_060_th_ut_001.vhd
     
    Objective: Verify that the file logical name MUST be an expression
               of type STRING.
    Test(s)  : rgrce_04_061_th_ng_001.vhd
     
    Objective: Verify that it is illegal to update a file object of 
               mode 'in'.
    Test(s)  : rgrce_04_063_in_es_000.vhd
               rgrce_04_063_in_es_002.vhd
     
    Objective: Verify that it is illegal to read a file object of 
               mode 'out'.
    Test(s)  : rgrce_04_063_in_es_001.vhd
     
    Objective: Verify that if a formal subprogram parameter is of a 
               file type, it must be associated with an actual that is 
               a file object.
    Test(s)  : rgrce_04_065_if_ct_000.vhd
     

4.4 Attribute Declarations

    Objective: Illegal to update predefined attribute S'DELAYED
    Test(s)  : rgrce_04_113_pr_ed_001.vhd
     
    Objective: Illegal to update predefined attribute S'STABLE
    Test(s)  : rgrce_04_113_pr_ed_002.vhd
     
    Objective: Illegal to update predefined attribute S'QUIET
    Test(s)  : rgrce_04_113_pr_ed_003.vhd
     
    Objective: Illegal to update predefined attribute S'TRANSACTION
    Test(s)  : rgrce_04_113_pr_ed_004.vhd
     

5.3 Disconnection Specification

    Objective: Verify that the disconnect specification's type must match
               that of the signal it is specifying it for.
    Test(s)  : rgrce_05_048_ad_nt_004.vhd
     
    Objective: Verify that the disconnect specification's type must exist.
    Test(s)  : rgrce_05_048_ad_nt_005.vhd
     
    Objective: Try mixing 'others' and 'all' in the same list.
    Test(s)  : rgrce_05_048_ad_nt_006.vhd
               rgrce_05_048_ad_nt_007.vhd
     
    Objective: Verify that a simple disconnection specification won't work
               with a non-guarded signal.
    Test(s)  : rgrce_05_050_if_ls_000.vhd
     
    Objective: Verify that a simple disconnection specification will not 
               work if the signal is not declared in the same declarative
               region.
    Test(s)  : rgrce_05_050_su_on_000.vhd
     
    Objective: Verify that an 'others' disconnection specification must
               be the last such disconnection specification in the
               declarative region for a particular type. 
    Test(s)  : rgrce_05_053_ad_on_000.vhd
               rgrce_05_053_ad_on_002.vhd
     
    Objective: Verify that an 'all' disconnection specification must
               be the last such disconnection specification in the
               declarative region for a particular type. 
    Test(s)  : rgrce_05_053_ad_on_001.vhd
     
    Objective: Verify that no guarded signal may be declared after a
               disconnect specification which uses 'others'.
    Test(s)  : rgrce_05_053_no_on_000.vhd
     
    Objective: Verify that no guarded signal may be declared after a
               disconnect specification which uses 'all'.
    Test(s)  : rgrce_05_053_no_on_001.vhd
     
    Objective: Verify that the time expression in a disconnection
               specification must be static.
    Test(s)  : rgrce_05_054_th_le_000.vhd
     
    Objective: Verify that it is an error for more than one disconnection
               specification to apply to the same signal.
    Test(s)  : rgrce_05_055_it_al_000.vhd
               rgrce_05_055_it_al_001.vhd
     

7.2.2 Relational Operators

    Objective: Test cases in which the relational operators are used to
               compare values whose types are different.  Each such 
               comparison should result in a semantic error.
    Test(s)  : rgrce_07_013_th_pe_000.vhd
     
    Objective: Test that file objects may not be compared legally with 
               either the "=" or "/=" operators.
    Test(s)  : rgrce_07_014_th_es_001.vhd

     
7.2.3 Adding Operators

    Objective: Verify that the operators "+" and "-" are not predefined for 
               all non-numeric types.  Every such expression should result
               in an error reported by the compiler.
    Test(s)  : rgrce_07_024_th_ng_001.vhd
     
    Objective: Verify that the operators "+" and "-" cannot legally operate 
               on numeric values of different types.  We will iterate
               through all different possible combinations of types and
               each expression should result in an error detected by the
               compiler.
    Test(s)  : rgrce_07_024_th_ng_003.vhd
     
    Objective: Verify that the signals "+" and "-" may not follow a
               multiplying operator, the exponentiating operator **, or 
               operators abs and not.  All statements within the
               process here should result in an error.
    Test(s)  : rgrce_07_030_be_ot_000.vhd
     

7.2.4 Multiplying Operators

    Objective: Verify that the operators mod and rem are not predefined ONLY
               for the type INTEGER.  All other types should result in an 
               error reported by the compiler.       
    Test(s)  : rgrce_07_032_fo_pe_001.vhd
     
    Objective: Verify that the operators mod and rem detect when their 
               boundaries have been passed.  All statements in this file 
               should result in simulation run-time errors detected by the 
               simulation kernel.
    Test(s)  : rgrce_07_032_fo_pe_002.vhd
     
    Objective: Verify that the operators "*" and "/" are not predefined for 
               all non-numeric types.  Every such expression should result
               in an error reported by the compiler.       
    Test(s)  : rgrce_07_032_th_ng_001.vhd
     
    Objective: Verify that the operators "*" and "/" are not predefined for 
               mixing floating point types with integer types.  Each such 
               expression within this file should result in an error.
    Test(s)  : rgrce_07_032_th_ng_002.vhd
     
    Objective: Verify that the operators "*" and "/" detect when their 
               boundaries have been passed.  All statements in this file 
               should result in simulation run-time errors detected by the 
               simulation kernel.
    Test(s)  : rgrce_07_032_th_ng_003.vhd
     
    Objective: Verify that certain incompatible operands may not be multiplied
               or divided, according to the table defined in the LRM.
               All expressions in this file should result in an error
               message by the VHDL compiler.
    Test(s)  : rgrce_07_036_in_pe_000.vhd
     
    Objective: Verify that the division of a physical type by an integer 
               constant of zero gets detected either by the analyzer or by 
               the simulator.
    Test(s)  : rgrce_07_039_di_on_002.vhd
     

7.2.5 Miscellaneous Operators

    Objective: Verify that the only types for which the ABS function is
               predefined are the numeric types.  Do this by attempting
               to apply the function to all other possible types.
    Test(s)  : rgrce_07_042_th_pe_001.vhd
     
    Objective: Verify that the only types for which exponentiation is
               predefined are the types INTEGER and REAL.  In addition,
               verify that the only legal type for the exponent is of
               type INTEGER.  All expressions within the process should
               result in a VHDL compilation error.
    Test(s)  : rgrce_07_043_th_er_000.vhd
     

8.1 Wait Statement

    Objective: Test wait statements.
               - If any of the [sensitivity_clause], [condition_clause],
                or [timeout_clause] is out of order, an error should be
                detected by the VHDL compiler.
    Test(s)  : rgrce_08_003_th_re_000.vhd
     
    Objective: Test wait statements.
               - If any of the clause keywords in the WAIT statement are
                misspelled, a helpful error message should be output by
                the VHDL compiler.
    Test(s)  : rgrce_08_003_th_re_001.vhd
     
    Objective: Test wait statements.
               - Test illegal semantics in the sensitivity_clause.  These
                are:
                1) Empty sensitivity list.
                2) Undefined signal in sensitivity list.
                3) Variable in a sensitivity list.
                4) Output port in a sensitivity list.  (they are read-only)
                5) Same signal multiple times in the sensitivity list.
    Test(s)  : rgrce_08_003_th_re_002.vhd
     
    Objective: Test wait statements.
               - Test illegal semantics in the condition_clause.  These
                are:
                1) Non-boolean expression.
                2) Undefined signal or variable in the condition.
    Test(s)  : rgrce_08_003_th_re_003.vhd
     
    Objective: Test wait statements.
               - Test illegal semantics in the timeout_clause.  These
                are:
                1) Non-time expression.
                2) Undefined signal or variable in the expression.
    Test(s)  : rgrce_08_003_th_re_004.vhd
     
    Objective: Verify that non-statically indexed signal names may NOT be
               used in the sensitivity_clause of a wait statement.
               All wait-statements in this file should cause VHDL compilation
               errors.
    Test(s)  : rgrce_08_004_ea_ed_001.vhd
     
    Objective: Verify that signals for which reading is NOT permitted may
               not be used in a wait statement's sensitivity_clause.
    Test(s)  : rgrce_08_004_ea_ed_002.vhd
     
    Objective: Make sure that it is an error if a wait statement appears in
               a function subprogram.
    Test(s)  : rgrce_08_010_it_am_000.vhd
     

8.2 Assertion Statement

    Objective: Make sure that the VHDL compiler detects when the condition in
               an assert statement is not of the predefined type BOOLEAN.
    Test(s)  : rgrce_08_011_an_ot_000.vhd
     
    Objective: Make sure that the VHDL compiler detects when the severity    
               clause of an assert statement comes before the report clause.
    Test(s)  : rgrce_08_011_an_ot_001.vhd
     
    Objective: Make sure that the VHDL compiler detects when the report
               clause of an assert statement is of the wrong type.
    Test(s)  : rgrce_08_012_if_ed_000.vhd
     
    Objective: Make sure that the VHDL compiler detects when the severity
               clause of an assert statement is of the wrong type.
    Test(s)  : rgrce_08_012_if_on_000.vhd
     

8.3 Signal Assignment Statement

    Objective: Syntax errors in signal assignment statements.
    Test(s)  : rgrce_08_020_as_ls_000.vhd
               rgrce_08_020_as_ls_001.vhd
     
    Objective: Semantic errors in signal assignment statements.
               Signal not found.
    Test(s)  : rgrce_08_020_as_ls_002.vhd
     
    Objective: Verify that the target of a signal assignment statement 
               must be a signal.  Each signal assignment statement in 
               this file should result in a compilation error.
    Test(s)  : rgrce_08_021_if_me_000.vhd
     
    Objective: Verify that the target of a signal assignment statement 
               must be of the same type as the value component of each 
               transaction in the expected output waveform.  Each signal 
               assignment statement should result in a compilation error.
    Test(s)  : rgrce_08_021_if_me_001.vhd
     
    Objective: Verify that each expression in the target aggregate must 
               be a locally static name which denotes a signal.
    Test(s)  : rgrce_08_022_fu_al_000.vhd
     
    Objective: Verify that the target of an aggregate signal assignment 
               statement must be determinable from the context, excluding 
               the aggregate itself, but including the fact that the type 
               of the aggregate must be a composite type.
    Test(s)  : rgrce_08_022_if_pe_000.vhd
     
    Objective: Verify that the base type of the value component of each 
               transaction produced by a waveform element on the right-hand 
               side of an aggregate signal assignment statement must be the 
               same as the base type of the aggregate which is being assigned.
               All signals assignments in this file should result in errors.
    Test(s)  : rgrce_08_022_th_te_000.vhd
     

8.3.1 Updating a Projected Output Waveform

    Objective: Illegal syntax for the waveform element portion of the signal
               assignment statement.
    Test(s)  : rgrce_08_025_th_ls_000.vhd
               rgrce_08_025_th_ls_001.vhd
               rgrce_08_025_th_ls_002.vhd
     
    Objective: Verify that it is illegal to assign the null waveform element
               to an element that is not a guarded signal.  Should result
               in a compilation error.
    Test(s)  : rgrce_08_026_it_al_000.vhd
     
    Objective: Test that the time expression in a waveform element may
               not evaluate to a negative value.
    Test(s)  : rgrce_08_027_it_ue_001.vhd
     
    Objective: Check that the base type of the time expression in each 
               waveform element must be the predefined physical type TIME 
               as defined in package standard.
    Test(s)  : rgrce_08_027_th_rd_000.vhd
     
    Objective: Test that the time expressions in a waveform must be in
               ascending order with respect to time.
    Test(s)  : rgrce_08_030_it_me_001.vhd

     
8.4 Variable Assignment Statement

    Objective: Verify that if the target of a variable assignment statement
               is a name, then the name must denote a variable.
    Test(s)  : rgrce_08_043_if_me_000.vhd
     
    Objective: Verify that the target of an aggregate variable assignment 
               statement must be determinable from the context, excluding 
               the aggregate itself, but including the fact that the type 
               of the aggregate must be a composite type.
    Test(s)  : rgrce_08_044_if_pe_000.vhd
     
    Objective: Verify that the base type of the expression on the right 
               hand side of an aggregate variable assignment statement must 
               be the same type as the base type of the aggregate which is 
               being assigned.  All variable assignments in this file should 
               result in errors.
    Test(s)  : rgrce_08_044_th_te_000.vhd
     

8.4.1 Array Variable Assignments

    Objective: Test that in a variable assignment statement involving
               arrays, both arrays must be the same size.
    Test(s)  : rgrce_08_054_th_sa_001.vhd

     
8.5 Procedure Call Statement

    Objective: Test syntax errors in procedure call statements:
                 o Empty actual parameter part.
                 o Illegal procedure name.
    Test(s)  : rgrce_08_055_ap_dy_001.vhd
     
    Objective: Test that a non-existent procedure gets detected.
    Test(s)  : rgrce_08_055_ap_dy_002.vhd
     

8.6 If Statement

    Objective: Test syntax errors in if statements.
    Test(s)  : rgrce_08_058_an_ns_000.vhd
               rgrce_08_058_an_ns_001.vhd
               rgrce_08_058_an_ns_002.vhd
               rgrce_08_058_an_ns_003.vhd
               rgrce_08_058_an_ns_004.vhd
               rgrce_08_058_an_ns_005.vhd
               rgrce_08_058_an_ns_006.vhd
     
    Objective: Make sure that all expressions in 'if' and 'elsif' clauses
               are of type BOOLEAN.
    Test(s)  : rgrce_08_059_an_an_000.vhd

     
9.1 Block Statement

    Objective: Verify that if no guard expression follows the reserved word
               'block', then a reference to GUARD results in an error.
    Test(s)  : rgrce_09_005_if_me_000.vhd
     
    Objective: Verify that the GUARD that gets implicitly declared as a
               result of a guard expression is a signal.  
    Test(s)  : rgrce_09_005_if_me_001.vhd
     
    Objective: Verify that a GUARD defined inside one block cannot be seen
               inside a block defined in the same declarative region.
    Test(s)  : rgrce_09_005_if_me_003.vhd
     
    Objective: Verify that a GUARD defined inside one block cannot be seen
               inside the block in which it is defined itself.
    Test(s)  : rgrce_09_005_if_me_004.vhd
     
    Objective: Try illegally using the GUARD signal in a signal assignment
               statement.
    Test(s)  : rgrce_09_006_th_ce_001.vhd
     
    Objective: Verify that if a label appears at the end of a block statement
               it must repeat the block label.
    Test(s)  : rgrce_09_008_if_el_000.vhd
     
    Objective: Verify that the value of signal GUARD does not implicitly
               extend to design entities bound to components instantiated
               within a block.  Should result in an error.
    Test(s)  : rgrce_09_009_th_ck_000.vhd
     
    Objective: Verify that an actual appearing in a port association list
               of a given block can never denote a formal port of the same
               block.
    Test(s)  : rgrce_09_010_an_ck_000.vhd
     

9.2 Process Statement

    Objective: Check to see that signals may NOT be declared inside
               of a process.
    Test(s)  : rgrce_09_011_ap_gn_002.vhd
     
    Objective: Check to see that components may NOT be declared inside
               of a process.
    Test(s)  : rgrce_09_011_ap_gn_003.vhd
     
    Objective: Check to see that config specifications may NOT be declared
               inside of a process.
    Test(s)  : rgrce_09_011_ap_gn_004.vhd
     
    Objective: Check to see that disconnection specifications may NOT be 
               declared inside of a process.
    Test(s)  : rgrce_09_011_ap_gn_005.vhd
     
    Objective: Check to see that block statements are illegal inside the
               body of a process.
    Test(s)  : rgrce_09_011_ap_gn_006.vhd
     
    Objective: Check to see that process statements are illegal inside the
               body of a process.
    Test(s)  : rgrce_09_011_ap_gn_007.vhd
     
    Objective: Check to see that component instantiation statements are 
               illegal inside the body of a process.
    Test(s)  : rgrce_09_011_ap_gn_008.vhd
     
    Objective: Test to see that a process statement with a sensitivity list
               following the reserved word process may not contain an
               explicit wait statement.
    Test(s)  : rgrce_09_012_su_le_000.vhd
     
    Objective: Verify that non-statically indexed signal names may NOT 
               be used in the sensitivity_list of a process statement.
               All process-statements in this file should cause VHDL 
               compilation errors.
    Test(s)  : rgrce_09_013_on_nt_001.vhd
     
    Objective: Verify that signals for which reading is NOT permitted may
               not be used in a process statement's sensitivity_list.
    Test(s)  : rgrce_09_013_on_nt_002.vhd
     
    Objective: Verify that if a label appears at the end of a process
               statement, it must repeat the process label.
    Test(s)  : rgrce_09_014_if_el_000.vhd
     
    Objective: Verify that all 'not-passive' processes, as defined in this 
               paragraph, may NOT appear in the entity statement part of an  
               entity declaration.
    Test(s)  : rgrce_09_016_su_on_001.vhd
     

9.5 Concurrent Signal Assignment Statement

    Objective: Verify that an error is reported if there is no explicitly      
               declared GUARD signal available, and the guarded signal
               assignment is outside of any block.
    Test(s)  : rgrce_09_037_th_nt_002.vhd
     
    Objective: Verify that it is an error if the target of a concurrent
               signal assignment is neither a guarded target nor an un-
               guarded target.
    Test(s)  : rgrce_09_038_it_et_000.vhd
     
    Objective: Verify that the explicitly-declared GUARD signal must be 
               of type BOOLEAN.
    Test(s)  : rgrce_09_039_th_nt_000.vhd
     
    Objective: Verify that an error is reported if there is no explicitly      
               or implicitly declared GUARD signal available.
    Test(s)  : rgrce_09_039_th_nt_001.vhd
     
    Objective: Verify that it is an error if the target of a concurrent 
               signal assignment statement is neither a guarded target nor 
               an unguarded target.
    Test(s)  : rgrce_09_040_it_et_000.vhd
     

10.1 Declarative Region

    Objective: Check that a declarative region is formed by the text of:
               "An entity declaration, together with a corresponding
               architecture body."
    Test(s)  : rgrce_10_003_an_dy_002.vhd
               rgrce_10_003_an_dy_003.vhd
               rgrce_10_003_an_dy_004.vhd
               rgrce_10_003_an_dy_005.vhd
     
    Objective: Check that a declarative region is formed by the text of:
               "A configuration declaration."
    Test(s)  : rgrce_10_004_ac_on_002.vhd
     
    Objective: Check that a declarative region is formed by the text of:
               "A subprogram declaration, together with the corresponding
               subprogram body."
    Test(s)  : rgrce_10_005_as_dy_003.vhd
               rgrce_10_005_as_dy_004.vhd
               rgrce_10_005_as_dy_005.vhd
               rgrce_10_005_as_dy_006.vhd
               rgrce_10_005_as_dy_007.vhd
               rgrce_10_005_as_dy_008.vhd
     
    Objective: Check that a declarative region is formed by the text of:
               "A package declaration, together with the corresponding
               body (if any)."
    Test(s)  : rgrce_10_006_ap_ny_002.vhd
               rgrce_10_006_ap_ny_003.vhd
               rgrce_10_006_ap_ny_004.vhd
     
    Objective: Check that a declarative region is formed by the text of:
               "A record type declaration."
    Test(s)  : rgrce_10_007_ar_on_002.vhd
     
    Objective: Check that a declarative region is formed by the text of:
               "A component declaration."
    Test(s)  : rgrce_10_008_ac_on_002.vhd
               rgrce_10_008_ac_on_003.vhd
     
    Objective: Check that a declarative region is formed by the text of:
               "A block statement."
    Test(s)  : rgrce_10_009_ab_nt_002.vhd
               rgrce_10_009_ab_nt_003.vhd
               rgrce_10_009_ab_nt_004.vhd
     
    Objective: Check that a declarative region is formed by the text of:
               "A process statement."
    Test(s)  : rgrce_10_010_ap_nt_002.vhd

     
10.4 Use Clauses

    Objective: An example to verify that following note from LRM
               is handled properly:
               
               If an entity X declared in package P is made potentially
               visible within a package Q (e.g., by the inclusion of the
               clause "use P.X;" in the context clause of package Q), and
               the context clause for design unit R includes the clause
               "use Q.all;", this does  not imply that X will be
               potentially visible in R.  Only those entities that are
               actually declared in package Q will be potentially 
               visible in design unit R (in the absence of any other
               use clauses).
    Test(s)  : rgrce_10_059_if_es_001.vhd

     
11.1 Design Units

    Objective: Test that a design file is comprised of ONE OR MORE 
               design units.
    Test(s)  : rgrce_11_002_on_le_000.vhd
     
    Objective: Test that a secondary units must be the separately 
               analyzed body of a primary units which has been previously 
               compiled.
    Test(s)  : rgrce_11_003_as_is_000.vhd
               rgrce_11_003_as_is_001.vhd
     

11.2 Design Libraries

    Objective: Try installing a library clause in a bad location.
    Test(s)  : rgrce_11_007_th_rs_000.vhd
     
    Objective: Verify that every design unit is assumed to contain the 
               following implicit context items as part of its context 
               clause:
                  library STD,WORK;  use STD.STANDARD.all;
    Test(s)  : rgrce_11_010_ev_se_002.vhd
               rgrce_11_010_ev_se_004.vhd
     

11.4 Order of Analysis

    Objective: Check that a primary unit whose name is referenced within a  
               given design unit must be analyzed prior to the analysis of
               the given design unit.
    Test(s)  : rgrce_11_020_ap_it_000.vhd
               rgrce_11_020_ap_it_001.vhd
               rgrce_11_020_ap_it_002.vhd

     
13.2 Lexical Elements, Separators, and Delimiters

    Objective: Test if a compound delimiter can contain a space
    Test(s)  : rgrce_13_014_ea_al_001.vhd

     
13.3 Identifiers

    Objective: Test if identifiers have a maximum length
    Test(s)  : rgrce_13_018_id_ds_001.vhd
     
    Objective: Test if leading underline allowed in identifier
    Test(s)  : rgrce_13_018_id_ds_002.vhd
     
    Objective: Test if consecutive underlines allowed in identifier
    Test(s)  : rgrce_13_018_id_ds_003.vhd
     
    Objective: Test if trailing underline allowed in identifier
    Test(s)  : rgrce_13_018_id_ds_004.vhd
     
    Objective: Test if special characters allowed in identifier
    Test(s)  : rgrce_13_018_id_ds_005.vhd
     
    Objective: Test case indifference in identifiers
    Test(s)  : rgrce_13_019_id_me_001.vhd
     
    Objective: Test case indifference in identifiers, one in the
               entity, the other in the architecture 
    Test(s)  : rgrce_13_019_id_me_002.vhd
     
    Objective: No space allowed in identifier, space is a separator
    Test(s)  : rgrce_13_020_no_or_001.vhd
           

13.4.1 Decimal Literals

    Objective: Test if leading decimal point permitted in real literals
    Test(s)  : rgrce_13_022_ad_en_001.vhd
           
    Objective: Test if trailing decimal point permitted in real literals
    Test(s)  : rgrce_13_022_ad_en_002.vhd
           
    Objective: Test if the underline character can be adjacent to a decimal
               point
    Test(s)  : rgrce_13_022_ad_en_003.vhd
                                                    
    Objective: Test if underline can lead an integer literal
    Test(s)  : rgrce_13_022_ad_en_004.vhd
                                                    
    Objective: Test if underline can lead a real literal
    Test(s)  : rgrce_13_022_ad_en_005.vhd
               
    Objective: Test if underline can be adjacent to itself in an integer literal
    Test(s)  : rgrce_13_022_ad_en_006.vhd
               
    Objective: Test if underline can be adjacent to itself in a real literal
    Test(s)  : rgrce_13_022_ad_en_007.vhd
               
    Objective: Test if underline can be adjacent to '.' in a real literal
    Test(s)  : rgrce_13_022_ad_en_008.vhd
               
    Objective: Test if underline can be adjacent on the left to 'E' in an 
               integer literal
    Test(s)  : rgrce_13_022_ad_en_009.vhd
                                                    
    Objective: Test if underline can trail an integer literal
    Test(s)  : rgrce_13_022_ad_en_011.vhd
               
    Objective: Test if underline can trail a real literal
    Test(s)  : rgrce_13_022_ad_en_012.vhd

    Objective: Test if two non-adjacent decimal points permitted in real 
               literals
    Test(s)  : rgrce_13_022_ad_en_013.vhd
           
    Objective: Test if two adjacent decimal points permitted in real literals
    Test(s)  : rgrce_13_022_ad_en_014.vhd
           
    Objective: Test if real exponent permitted in real literals
    Test(s)  : rgrce_13_022_ad_en_015.vhd
           
    Objective: Test if double (+) permitted in the exponents of real
               literals
    Test(s)  : rgrce_13_022_ad_en_016.vhd
                                                    
    Objective: Test if double (-) permitted in the exponents of real
               literals
    Test(s)  : rgrce_13_022_ad_en_017.vhd
                                                    
    Objective: Test if underline permitted in exponent in real literal
    Test(s)  : rgrce_13_022_ad_en_018.vhd
               
    Objective: Test if underline can be adjacent on the right to 'E' in an 
               integer literal
    Test(s)  : rgrce_13_022_as_en_010.vhd
                                                    
    Objective: Test if the exponent for an integer literal can have a 
               minus sign
    Test(s)  : rgrce_13_024_an_gn_001.vhd
     
    Objective: No imbedded spaces in literals
    Test(s)  : rgrce_13_025_no_or_001.vhd
               
    Objective: Test if a space is allowed in an integer literal
    Test(s)  : rgrce_13_025_no_or_002.vhd
     

13.4.2 Based Literals

    Objective: Base cannot be less than two
    Test(s)  : rgrce_13_026_th_en_001.vhd
               
    Objective: Base cannot be more than sixteen
    Test(s)  : rgrce_13_026_th_en_002.vhd
               
    Objective: Invalid hex digit in literal
    Test(s)  : rgrce_13_027_th_en_001.vhd
               
    Objective: Extended digits allowed in the base of a based literal
    Test(s)  : rgrce_13_027_th_on_001.vhd
               
    Objective: Extended digits allowed in the exponent of a based literal
    Test(s)  : rgrce_13_027_th_on_002.vhd
               
    Objective: Test the case where the extended digit is not less than the base
    Test(s)  : rgrce_13_028_th_se_001.vhd


13.5 Character Literals

    Objective: Character literals are one character long
    Test(s)  : rgrce_13_029_ac_rs_001.vhd
               
    Objective: Test '' (double ') as a character literal 
    Test(s)  : rgrce_13_029_ac_rs_002.vhd
           
    Objective: Test null as a character literal 
    Test(s)  : rgrce_13_029_ac_rs_003.vhd

           
13.6 String Literals

    Objective: Test if a single " accepted as a string literal 
    Test(s)  : rgrce_13_031_if_al_001.vhd

           
13.7 Bit String Literals

    Objective: Bit-string literal of base O (octal) only use 0 through 7
    Test(s)  : rgrce_13_036_if_gh_001.vhd
               
    Objective: Bit-string literal of base X only use 0 through 9 and 
               A through F
    Test(s)  : rgrce_13_036_if_hf_001.vhd
               
    Objective: Bit-string literal of base B only use 0 and 1
    Test(s)  : rgrce_13_036_if_nd_001.vhd

               
13.9 Reserved Words

    Objective: Test if reserved word abs can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_001.vhd
               
    Objective: Test if reserved word access can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_002.vhd
               
    Objective: Test if reserved word after can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_003.vhd
               
    Objective: Test if reserved word alias can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_004.vhd
               
    Objective: Test if reserved word all can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_005.vhd
               
    Objective: Test if reserved word and can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_006.vhd
               
    Objective: Test if reserved word architecture can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_007.vhd
               
    Objective: Test if reserved word array can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_008.vhd
               
    Objective: Test if reserved word assert can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_009.vhd
               
    Objective: Test if reserved word attribute can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_010.vhd
               
    Objective: Test if reserved word begin can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_011.vhd
               
    Objective: Test if reserved word block can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_012.vhd
               
    Objective: Test if reserved word body can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_013.vhd
               
    Objective: Test if reserved word buffer can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_014.vhd
               
    Objective: Test if reserved word bus can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_015.vhd
               
    Objective: Test if reserved word case can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_016.vhd
               
    Objective: Test if reserved word component can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_017.vhd
               
    Objective: Test if reserved word configuration can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_018.vhd
               
    Objective: Test if reserved word constant can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_019.vhd
               
    Objective: Test if reserved word disconnect can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_020.vhd
               
    Objective: Test if reserved word downto can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_021.vhd
               
    Objective: Test if reserved word else can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_022.vhd
               
    Objective: Test if reserved word elsif can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_023.vhd
               
    Objective: Test if reserved word end can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_024.vhd
               
    Objective: Test if reserved word entity can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_025.vhd
               
    Objective: Test if reserved word exit can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_026.vhd
               
    Objective: Test if reserved word file can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_027.vhd
               
    Objective: Test if reserved word for can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_028.vhd
               
    Objective: Test if reserved word function can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_029.vhd
               
    Objective: Test if reserved word generate can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_030.vhd
               
    Objective: Test if reserved word generic can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_031.vhd
               
    Objective: Test if reserved word guarded can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_032.vhd
               
    Objective: Test if reserved word if can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_033.vhd
               
    Objective: Test if reserved word in can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_034.vhd
               
    Objective: Test if reserved word inout can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_035.vhd
               
    Objective: Test if reserved word is can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_036.vhd
               
    Objective: Test if reserved word label can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_037.vhd
               
    Objective: Test if reserved word library can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_038.vhd
               
    Objective: Test if reserved word linkage can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_039.vhd
               
    Objective: Test if reserved word loop can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_040.vhd
               
    Objective: Test if reserved word map can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_041.vhd
               
    Objective: Test if reserved word mod can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_042.vhd
               
    Objective: Test if reserved word nand can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_043.vhd
               
    Objective: Test if reserved word new can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_044.vhd
               
    Objective: Test if reserved word next can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_045.vhd
               
    Objective: Test if reserved word nor can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_046.vhd
               
    Objective: Test if reserved word not can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_047.vhd
               
    Objective: Test if reserved word null can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_048.vhd
               
    Objective: Test if reserved word of can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_049.vhd
               
    Objective: Test if reserved word on can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_050.vhd
               
    Objective: Test if reserved word open can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_051.vhd
               
    Objective: Test if reserved word or can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_052.vhd
               
    Objective: Test if reserved word others can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_053.vhd
               
    Objective: Test if reserved word out can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_054.vhd
               
    Objective: Test if reserved word package can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_055.vhd
               
    Objective: Test if reserved word port can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_056.vhd
               
    Objective: Test if reserved word procedure can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_057.vhd
               
    Objective: Test if reserved word process can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_058.vhd
               
    Objective: Test if reserved word range can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_059.vhd
               
    Objective: Test if reserved word record can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_060.vhd
               
    Objective: Test if reserved word register can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_061.vhd
               
    Objective: Test if reserved word rem can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_062.vhd
               
    Objective: Test if reserved word report can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_063.vhd
               
    Objective: Test if reserved word return can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_064.vhd
               
    Objective: Test if reserved word select can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_065.vhd
               
    Objective: Test if reserved word severity can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_066.vhd
               
    Objective: Test if reserved word signal can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_067.vhd
               
    Objective: Test if reserved word subtype can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_068.vhd
               
    Objective: Test if reserved word then can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_069.vhd
               
    Objective: Test if reserved word to can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_070.vhd
               
    Objective: Test if reserved word transport can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_071.vhd
               
    Objective: Test if reserved word type can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_072.vhd
               
    Objective: Test if reserved word units can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_073.vhd
               
    Objective: Test if reserved word until can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_074.vhd
               
    Objective: Test if reserved word use can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_075.vhd
               
    Objective: Test if reserved word variable can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_076.vhd
               
    Objective: Test if reserved word wait can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_077.vhd
               
    Objective: Test if reserved word when can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_078.vhd
               
    Objective: Test if reserved word while can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_079.vhd
               
    Objective: Test if reserved word with can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_080.vhd
               
    Objective: Test if reserved word xor can be used as an identifier
    Test(s)  : rgrce_13_042_ar_er_081.vhd
               

13.10 Allowable Replacements of Characters

    Objective: Test if only 1 (#) can be replaced with (:) in 
               based literals
    Test(s)  : rgrce_13_046_th_es_001.vhd
                                                    
    Objective: Test if (%) is a valid string character in a string 
               string literal after (") replaced by (%)
    Test(s)  : rgrce_13_047_an_ue_001.vhd
                                                    
    Objective: Test if only 1 (") can be replaced by (%) in 
               string literals
    Test(s)  : rgrce_13_047_th_ed_001.vhd
                                                    
    Objective: Test if (") is a valid string character in a string 
               literal after (") replaced by (%)
    Test(s)  : rgrce_13_047_th_ed_002.vhd
                                                    
    Objective: Test if only 1 (") can be replaced by (%) in bit
               string literals
    Test(s)  : rgrce_13_047_th_ed_003.vhd


