VHDL essentials

Xilinx report

VHDL implementation of a multisensor receiver

prepared by P. Bakowski

This pages contain the report generated by Xilinx tools for the implementation of the circuit in XC3000 FPGA.

PPR RESULTS FOR DESIGN LMS_FINAL_P

From PPR Version 5.2.0

1997/06/19 12:25:18

Xilinx, Inc.

Table of Contents

-----------------

List of Warnings ................................................. 1

Device Utilization ............................................... 2

Implementation Options ........................................... 3

Xact Performance Summary ......................................... 4

Chip Pinout Description .......................................... 5

Routing Summary .................................................. 12

Information in Other Reports ..................................... 21

List of Warnings

----------------

*** PPR: WARNING 5527:

The design uses no global buffers (BUFGS or BUFGP). Their use can

improve performance for clocks or widely distributed signals.

*** PPR: WARNING 7028:

The design has flip-flops with asynchronous set/reset controls (PRE/SD

or CLR/RD pins). When PPR analyzes design timing, it does not trace

paths through the asynchronous set/reset input and on through the Q

output.

If you want PPR to control the delay on paths through asynchronous

set/reset pins, you must split the delay requirement into two

segments: one ending at the set/reset input, and the other beginning

at the flip-flop output.

If you want PPR not to analyze paths that lead to asynchronous

set/reset pins, attach an IGNORE specification to the pin(s) or

signal(s).

By default, XDelay reports all paths through asynchronous set/reset

pins. To prevent XDelay from showing these paths, use FlagBlk

CLB_Disable_SR_Q on the appropriate flip-flops.

Device Utilization

------------------

Partitioned Design Utilization Using Part 4013PG223-3

-----------------------------------------------------------------

No. Used Max Available %Used

-----------------------------------------------------------------

Occupied CLBs 576 576 100%

Bonded I/O Pins 110 192 57%

F and G Function Generators (*) 1142 1152 99%

H Function Generators 61 576 10%

CLB Flip Flops 419 1152 36%

IOB Input Flip Flops 0 192 0%

IOB Output Flip Flops 0 192 0%

3-State Buffers 0 1248 0%

3-State Half Longlines 0 96 0%

Edge Decode Inputs 0 288 0%

Edge Decode Half Longlines 0 32 0%

(*) If RAM/ROM elements are present in the design, this count

includes the function generators used for them. A 16x1 memory uses 1

function generator; a 32x1 uses two.

----------------------------------------------------------------

CPU Times

CPU time taken for Partition: 0 hrs 2 mins 29 secs

CPU time taken for Placement: 0 hrs 29 mins 11 secs

Implementation Options

----------------------

PPR Parameters

Design = lms_final_p.xtf

Logfile = ppr.log

Outfile =

Estimate = FALSE

Additional Specified or Non-Default Parameters

parttype = 4013PG223-3

cstfile = lms_final_p

seed = 866719192

Xact Performance Summary

------------------------

Parttype Used : 4013PG223

Speed Grade : -3

End-

Limit Actual Points

(ns) * (ns) Missed Specification

------ ------ ------- -------------

127.7 0/823 DEFAULT_FROM_FFS_TO_FFS=FROM:ffs:TO:ffs

34.5 0/882 DEFAULT_FROM_PADS_TO_FFS=FROM:pads:TO:ffs

17.4 0/48 DEFAULT_FROM_FFS_TO_PADS=FROM:ffs:TO:pads

(*) Use the -FailedSpec and/or -TSMaxPaths options of the

XDelay-TimeSpec command, accessible through the XDE or XDelay program,

to confirm the actual path delays computed by PPR. Note that

XDelay-TimeSpec will not report paths that start and end in the same

block (CLB or IOB) and use no external routing.

*** PPR: WARNING 7028:

The design has flip-flops with asynchronous set/reset controls (PRE/SD

or CLR/RD pins). When PPR analyzes design timing, it does not trace

paths through the asynchronous set/reset input and on through the Q

output.

If you want PPR to control the delay on paths through asynchronous

set/reset pins, you must split the delay requirement into two

segments: one ending at the set/reset input, and the other beginning

at the flip-flop output. If you want PPR not to analyze paths that

lead to asynchronous set/reset pins, attach an IGNORE specification to

the pin(s) or signal(s).

By default, XDelay reports all paths through asynchronous set/reset

pins. To prevent XDelay from showing these paths, use FlagBlk

CLB_Disable_SR_Q on the appropriate flip-flops.

Chip Pinout Description

-----------------------

This chapter describes where your design's pins were placed in termsof the package pins. Generally there are four sections for this chapter.

The first section is a list showing signal name and the package pin location, sorted by the signal name.

The second section is a list showing the package pin names and signal names sorted by the

package pin names.

Next section appears only if your design uses special pads.

This will a table showing the special pad names and the

signal names, sorted by special pad name.

The last section is a series of CST file statements, which if copied into a text file, can be used

as constraints for a subsequent ppr run for locking IOs at their current locations.

Sorted by Signal Names:

Pin Name Package Pin Location

-------- --------------------

CLK : A10

ENTREE_1<0> : K1

ENTREE_1<1> : L1

ENTREE_1<2> : N1

ENTREE_1<3> : P1

ENTREE_1<4> : R1

ENTREE_1<5> : T1

ENTREE_1<6> : L2

ENTREE_1<7> : N2

ENTREE_2<0> : P2

ENTREE_2<1> : R2

ENTREE_2<2> : L3

ENTREE_2<3> : P3

ENTREE_2<4> : C9

ENTREE_2<5> : C10

ENTREE_2<6> : L4

ENTREE_2<7> : M4

ENTREE_3<0> : N4

ENTREE_3<1> : P4

ENTREE_3<2> : U4

ENTREE_3<3> : V4

ENTREE_3<4> : R5

ENTREE_3<5> : T5

ENTREE_3<6> : U5

ENTREE_3<7> : V5

ENTREE_4<0> : R6

ENTREE_4<1> : T6

ENTREE_4<2> : U6

ENTREE_4<3> : V6

ENTREE_4<4> : R8

ENTREE_4<5> : T8

ENTREE_4<6> : U8

ENTREE_4<7> : V8

ENTREE_5<0> : V9

ENTREE_5<1> : T10

ENTREE_5<2> : R11

ENTREE_5<3> : T11

ENTREE_5<4> : U11

ENTREE_5<5> : V11

ENTREE_5<6> : R12

ENTREE_5<7> : R13

Pin Name Package Pin Location (continued)

-------- --------------------

ENTREE_6<0> : B1

ENTREE_6<1> : C1

ENTREE_6<2> : D1

ENTREE_6<3> : E1

ENTREE_6<4> : F1

ENTREE_6<5> : H1

ENTREE_6<6> : J1

ENTREE_6<7> : E2

ENTREE_7<0> : E3

ENTREE_7<1> : F3

ENTREE_7<2> : H3

ENTREE_7<3> : A4

ENTREE_7<4> : E4

ENTREE_7<5> : F4

ENTREE_7<6> : G4

ENTREE_7<7> : H4

ENTREE_7<8> : J3

ENTREE_7<9> : A5

ENTREE_7<10> : B5

ENTREE_7<11> : C5

RESET<0> : C11

SORTIE_1<0> : B18

SORTIE_1<1> : C18

SORTIE_1<2> : D18

SORTIE_1<3> : E18

SORTIE_1<4> : F18

SORTIE_1<5> : G18

SORTIE_1<6> : H18

SORTIE_1<7> : J18

SORTIE_1<8> : A17

SORTIE_1<9> : C17

SORTIE_1<10> : D17

SORTIE_1<11> : F17

SORTIE_2<0> : A16

SORTIE_2<1> : A15

SORTIE_2<2> : A14

SORTIE_2<3> : A13

SORTIE_2<4> : A12

SORTIE_2<5> : A11

SORTIE_2<6> : B9

SORTIE_2<7> : B10

SORTIE_2<8> : B11

SORTIE_2<9> : B12

SORTIE_2<10> : B13

SORTIE_2<11> : B14

SORTIE_3<0> : K18

SORTIE_3<1> : L18

SORTIE_3<2> : M18

SORTIE_3<3> : N18

SORTIE_3<4> : P18

SORTIE_3<5> : R18

SORTIE_3<6> : T18

SORTIE_3<7> : U18

SORTIE_3<8> : J17

SORTIE_3<9> : K17

SORTIE_3<10> : L17

SORTIE_3<11> : M17

SORTIE_4<0> : N17

PPR RESULTS FOR DESIGN LMS_FINAL_P Page 7

Pin Name Package Pin Location (continued)

-------- --------------------

SORTIE_4<1> : P17

SORTIE_4<2> : R17

SORTIE_4<3> : T17

SORTIE_4<4> : E15

SORTIE_4<5> : F15

SORTIE_4<6> : G15

SORTIE_4<7> : H15

SORTIE_4<8> : L15

SORTIE_4<9> : M15

SORTIE_4<10> : N15

SORTIE_4<11> : P15

Sorted by Package Pin Locations:

Package Pin Location Pin Name

-------------------- --------

A4 : ENTREE_7<3>

A5 : ENTREE_7<9>

A10 : CLK

A11 : SORTIE_2<5>

A12 : SORTIE_2<4>

A13 : SORTIE_2<3>

A14 : SORTIE_2<2>

A15 : SORTIE_2<1>

A16 : SORTIE_2<0>

A17 : SORTIE_1<8>

B1 : ENTREE_6<0>

B5 : ENTREE_7<10>

B9 : SORTIE_2<6>

B10 : SORTIE_2<7>

B11 : SORTIE_2<8>

B12 : SORTIE_2<9>

B13 : SORTIE_2<10>

B14 : SORTIE_2<11>

B18 : SORTIE_1<0>

C1 : ENTREE_6<1>

C5 : ENTREE_7<11>

C9 : ENTREE_2<4>

C10 : ENTREE_2<5>

C11 : RESET<0>

C17 : SORTIE_1<9>

C18 : SORTIE_1<1>

D1 : ENTREE_6<2>

D17 : SORTIE_1<10>

D18 : SORTIE_1<2>

E1 : ENTREE_6<3>

E2 : ENTREE_6<7>

E3 : ENTREE_7<0>

E4 : ENTREE_7<4>

E15 : SORTIE_4<4>

E18 : SORTIE_1<3>

F1 : ENTREE_6<4>

F3 : ENTREE_7<1>

F4 : ENTREE_7<5>

F15 : SORTIE_4<5>

F17 : SORTIE_1<11>

F18 : SORTIE_1<4>

G4 : ENTREE_7<6>

Package Pin Location Pin Name (continued)

-------------------- --------

G15 : SORTIE_4<6>

G18 : SORTIE_1<5>

H1 : ENTREE_6<5>

H3 : ENTREE_7<2>

H4 : ENTREE_7<7>

H15 : SORTIE_4<7>

H18 : SORTIE_1<6>

J1 : ENTREE_6<6>

J3 : ENTREE_7<8>

J17 : SORTIE_3<8>

J18 : SORTIE_1<7>

K1 : ENTREE_1<0>

K17 : SORTIE_3<9>

K18 : SORTIE_3<0>

L1 : ENTREE_1<1>

L2 : ENTREE_1<6>

L3 : ENTREE_2<2>

L4 : ENTREE_2<6>

L15 : SORTIE_4<8>

L17 : SORTIE_3<10>

L18 : SORTIE_3<1>

M4 : ENTREE_2<7>

M15 : SORTIE_4<9>

M17 : SORTIE_3<11>

M18 : SORTIE_3<2>

N1 : ENTREE_1<2>

N2 : ENTREE_1<7>

N4 : ENTREE_3<0>

N15 : SORTIE_4<10>

N17 : SORTIE_4<0>

N18 : SORTIE_3<3>

P1 : ENTREE_1<3>

P2 : ENTREE_2<0>

P3 : ENTREE_2<3>

P4 : ENTREE_3<1>

P15 : SORTIE_4<11>

P17 : SORTIE_4<1>

P18 : SORTIE_3<4>

R1 : ENTREE_1<4>

R2 : ENTREE_2<1>

R5 : ENTREE_3<4>

R6 : ENTREE_4<0>

R8 : ENTREE_4<4>

R11 : ENTREE_5<2>

R12 : ENTREE_5<6>

R13 : ENTREE_5<7>

R17 : SORTIE_4<2>

R18 : SORTIE_3<5>

T1 : ENTREE_1<5>

T5 : ENTREE_3<5>

T6 : ENTREE_4<1>

T8 : ENTREE_4<5>

T10 : ENTREE_5<1>

T11 : ENTREE_5<3>

T17 : SORTIE_4<3>

T18 : SORTIE_3<6>

U4 : ENTREE_3<2>

U5 : ENTREE_3<6>

Package Pin Location Pin Name (continued)

-------------------- --------

U6 : ENTREE_4<2>

U8 : ENTREE_4<6>

U11 : ENTREE_5<4>

U18 : SORTIE_3<7>

V4 : ENTREE_3<3>

V5 : ENTREE_3<7>

V6 : ENTREE_4<3>

V8 : ENTREE_4<7>

V9 : ENTREE_5<0>

V11 : ENTREE_5<5>

CST File Format (location constraints file):

place instance clk_pad : A10 ;

place instance entree_1<0>_pad : K1 ;

place instance entree_1<1>_pad : L1 ;

place instance entree_1<2>_pad : N1 ;

place instance entree_1<3>_pad : P1 ;

place instance entree_1<4>_pad : R1 ;

place instance entree_1<5>_pad : T1 ;

place instance entree_1<6>_pad : L2 ;

place instance entree_1<7>_pad : N2 ;

place instance entree_2<0>_pad : P2 ;

place instance entree_2<1>_pad : R2 ;

place instance entree_2<2>_pad : L3 ;

place instance entree_2<3>_pad : P3 ;

place instance entree_2<4>_pad : C9 ;

place instance entree_2<5>_pad : C10 ;

place instance entree_2<6>_pad : L4 ;

place instance entree_2<7>_pad : M4 ;

place instance entree_3<0>_pad : N4 ;

place instance entree_3<1>_pad : P4 ;

place instance entree_3<2>_pad : U4 ;

place instance entree_3<3>_pad : V4 ;

place instance entree_3<4>_pad : R5 ;

place instance entree_3<5>_pad : T5 ;

place instance entree_3<6>_pad : U5 ;

place instance entree_3<7>_pad : V5 ;

place instance entree_4<0>_pad : R6 ;

place instance entree_4<1>_pad : T6 ;

place instance entree_4<2>_pad : U6 ;

place instance entree_4<3>_pad : V6 ;

place instance entree_4<4>_pad : R8 ;

place instance entree_4<5>_pad : T8 ;

place instance entree_4<6>_pad : U8 ;

place instance entree_4<7>_pad : V8 ;

place instance entree_5<0>_pad : V9 ;

place instance entree_5<1>_pad : T10 ;

place instance entree_5<2>_pad : R11 ;

place instance entree_5<3>_pad : T11 ;

place instance entree_5<4>_pad : U11 ;

place instance entree_5<5>_pad : V11 ;

place instance entree_5<6>_pad : R12 ;

place instance entree_5<7>_pad : R13 ;

place instance entree_6<0>_pad : B1 ;

place instance entree_6<1>_pad : C1 ;

place instance entree_6<2>_pad : D1 ;

place instance entree_6<3>_pad : E1 ;

place instance entree_6<4>_pad : F1 ;

place instance entree_6<5>_pad : H1 ;

place instance entree_6<6>_pad : J1 ;

place instance entree_6<7>_pad : E2 ;

place instance entree_7<0>_pad : E3 ;

place instance entree_7<1>_pad : F3 ;

place instance entree_7<2>_pad : H3 ;

place instance entree_7<3>_pad : A4 ;

place instance entree_7<4>_pad : E4 ;

place instance entree_7<5>_pad : F4 ;

place instance entree_7<6>_pad : G4 ;

place instance entree_7<7>_pad : H4 ;

place instance entree_7<8>_pad : J3 ;

place instance entree_7<9>_pad : A5 ;

place instance entree_7<10>_pad : B5 ;

place instance entree_7<11>_pad : C5 ;

place instance reset<0>_pad : C11 ;

place instance sortie_1<0>_pad : B18 ;

place instance sortie_1<1>_pad : C18 ;

place instance sortie_1<2>_pad : D18 ;

place instance sortie_1<3>_pad : E18 ;

place instance sortie_1<4>_pad : F18 ;

place instance sortie_1<5>_pad : G18 ;

place instance sortie_1<6>_pad : H18 ;

place instance sortie_1<7>_pad : J18 ;

place instance sortie_1<8>_pad : A17 ;

place instance sortie_1<9>_pad : C17 ;

place instance sortie_1<10>_pad : D17 ;

place instance sortie_1<11>_pad : F17 ;

place instance sortie_2<0>_pad : A16 ;

place instance sortie_2<1>_pad : A15 ;

place instance sortie_2<2>_pad : A14 ;

place instance sortie_2<3>_pad : A13 ;

place instance sortie_2<4>_pad : A12 ;

place instance sortie_2<5>_pad : A11 ;

place instance sortie_2<6>_pad : B9 ;

place instance sortie_2<7>_pad : B10 ;

place instance sortie_2<8>_pad : B11 ;

place instance sortie_2<9>_pad : B12 ;

place instance sortie_2<10>_pad : B13 ;

place instance sortie_2<11>_pad : B14 ;

place instance sortie_3<0>_pad : K18 ;

place instance sortie_3<1>_pad : L18 ;

place instance sortie_3<2>_pad : M18 ;

place instance sortie_3<3>_pad : N18 ;

place instance sortie_3<4>_pad : P18 ;

place instance sortie_3<5>_pad : R18 ;

place instance sortie_3<6>_pad : T18 ;

place instance sortie_3<7>_pad : U18 ;

place instance sortie_3<8>_pad : J17 ;

place instance sortie_3<9>_pad : K17 ;

place instance sortie_3<10>_pad : L17 ;

place instance sortie_3<11>_pad : M17 ;

place instance sortie_4<0>_pad : N17 ;

place instance sortie_4<1>_pad : P17 ;

place instance sortie_4<2>_pad : R17 ;

place instance sortie_4<3>_pad : T17 ;

place instance sortie_4<4>_pad : E15 ;

place instance sortie_4<5>_pad : F15 ;

place instance sortie_4<6>_pad : G15 ;

place instance sortie_4<7>_pad : H15 ;

place instance sortie_4<8>_pad : L15 ;

place instance sortie_4<9>_pad : M15 ;

place instance sortie_4<10>_pad : N15 ;

place instance sortie_4<11>_pad : P15 ;

Routing Summary

---------------

Number of unrouted connections : 0

CPU time taken for Routing : 1 hrs 11 mins 37 secs

Split Nets:

The list below identifies those signals which were routed through CLBs

or other blocks. In XDE and XDelay reports, these signals will have

two or more segments. An underscore (_) and a number will be added to

the end of the original signal name to identify the different

segments. To analyze all segments of a signal in XDelay or QueryNet

reports, append the original name with "_*" when prompted for a signal

name.

PPR may route signals through CLBs or other blocks in any of the

following situations:

* The delay on a signal might be reduced by routing it through a CLB,

given the extra flexibility in routing resources and the reduced

capacitive loading on the signal. PPR takes this into consideration.

* The delay on a signal might be reduced by sourcing it from two block

outputs instead of one, which is possible in some block

configurations. PPR will do this where possible.

* A signal on a global buffer may not be able to connect directly to a

load pin, given the placement of that load pin and the other global

resources which are used. PPR will pass the signal through another CLB

and route the load pin using general-purpose interconnect.

* In an XC4000 design, A BUFGP can be sourced only from an IOB. If the

design indicates that a BUFGP is driven from an internal source, PPR

will route the signal through the output path of the IOB in order to

access the BUFGP input.

Segments Original Signal Name

2 imult7_e2_1<7>

3 imult7_e2_1<3>

2 imult7_e2_1<1>

3 i2_mult_7_mult_s1<0>

2 i2_mult_7_mult_s1<2>

2 i2_mult_7/smult_booth_rip1/u739_O

2 i2_mult_7_mult_s1<3>

3 i2_mult_7/smult_booth_rip1/u719_O

2 i2_mult_7/smult_booth_rip1/u704_O

Split Nets:

2 i2_mult_7/smult_booth_rip1/u702_O

2 i2_mult_7/smult_booth_rip1/u676_O

2 i2_mult_7/smult_booth_rip1/u630_O

2 i2_mult_7/smult_booth_rip1/u618_O

2 i2_mult_7/smult_booth_rip1/u589_O

2 imult7_e2_2<7>

2 i2_mult_7/smult_booth_rip1/u468_O

3 imult7_e2_2<5>

4 imult7_e2_2<4>

2 imult7_e2_2<3>

2 imult7_e2_2<2>

2 i2_mult_7/smult_booth_rip1/u92_O

2 i2_mult_7/smult_booth_rip1/u230_O

2 imult7_e1_1<5>

2 imult7_e1_1<7>

2 imult7_e1_1<3>

2 imult7_e1_1<1>

2 i1_mult_7_mult_s1<1>

3 i1_mult_7/smult_booth_rip1/u743_O

3 i1_mult_7/smult_booth_rip1/u737_O

2 i1_mult_7/smult_booth_rip1/u717_O

2 i1_mult_7/smult_booth_rip1/u709_O

2 i1_mult_7/smult_booth_rip1/u699_O

2 i1_mult_7/smult_booth_rip1/u580_O

2 i1_mult_7/smult_booth_rip1/u526_O

2 imult7_e1_2<7>

2 i1_mult_7/smult_booth_rip1/u123_O

3 imult7_e1_2<6>

2 i1_mult_7/smult_booth_rip1/u533_O

Split Nets:

2 i1_mult_7/smult_booth_rip1/u40_O

2 imult7_e1_2<4>

3 i1_mult_7/smult_booth_rip1/u318_O

2 imult7_e1_2<3>

2 imult7_e1_2<2>

2 i1_mult_7/smult_booth_rip1/u9_O

4 imult7_e1_2<1>

2 imult7_e1_2<0>

2 imult7_e1_1<0>

3 i1_sub_8_sub_s1<4>

2 i1_sub_8/sub_rip1/u95_O

2 i1_e_lms_final_sub8_e1_2<9>

3 i1_e_lms_final_sub8_e1_2<4>

2 i1_add_6_add_s1<1>

3 i1_add_6/add_rip1/u9_O

2 i1_add_6/add_rip1/u35_O

2 i1_add_6/add_rip1/u56_O

2 i1_add_6/add_rip1/u51_O

3 i1_add_6/add_rip1/u72_O

2 i1_add_6/add_rip1/u99_O

2 i1_add_6/add_rip1/u96_O

3 i1_add_6/add_rip1/u91_O

3 iadd6_e1_1<10>

2 iadd6_e1_2<10>

3 iadd6_e1_1<9>

3 iadd6_e1_2<9>

2 iadd6_e1_1<8>

3 iadd6_e1_1<5>

Split Nets:

3 iadd6_e1_2<5>

2 iadd6_e1_2<3>

3 iadd6_e1_1<1>

3 imult4_e1_1<9>

3 imult4_e1_1<11>

2 imult4_e1_1<7>

3 imult4_e1_1<5>

2 i1_mult_4_mult_s1<1>

2 i1_mult_4/smult_booth_rip1/u1716_O

2 i1_mult_4/smult_booth_rip1/u1686_O

3 i1_mult_4/smult_booth_rip1/u1671_O

2 i1_mult_4/smult_booth_rip1/u1651_O

2 i1_mult_4/smult_booth_rip1/u1581_O

2 i1_mult_4/smult_booth_rip1/u1171_O

2 i1_mult_4/smult_booth_rip1/u1293_O

2 i1_mult_4/smult_booth_rip1/u1494_O

2 i1_mult_4/smult_booth_rip1/u1185_O

2 i1_mult_4/smult_booth_rip1/u1400_O

2 i1_mult_4/smult_booth_rip1/u1302_O

2 i1_mult_4/smult_booth_rip1/u1240_O

2 i1_mult_4/smult_booth_rip1/u1290_O

3 imult4_e1_2<11>

2 i1_mult_4/smult_booth_rip1/u1367_O

2 imult4_e1_2<10>

2 i1_mult_4/smult_booth_rip1/u264_O

3 imult4_e1_2<9>

2 i1_mult_4/smult_booth_rip1/u1081_O

2 i1_mult_4/smult_booth_rip1/u1078_O

2 i1_mult_4/smult_booth_rip1/u92_O

Split Nets:

2 i1_mult_4/smult_booth_rip1/u1122_O

2 imult4_e1_2<7>

3 i1_mult_4/smult_booth_rip1/u652_O

2 i1_mult_4/smult_booth_rip1/u909_O

2 i1_mult_4/smult_booth_rip1/u823_O

2 imult4_e1_2<6>

3 imult4_e1_2<5>

2 i1_mult_4/smult_booth_rip1/u935_O

2 imult4_e1_2<4>

2 imult4_e1_2<3>

2 i1_mult_4/smult_booth_rip1/u615_O

3 imult4_e1_2<2>

2 i1_mult_4/smult_booth_rip1/u669_O

2 i1_mult_4/smult_booth_rip1/u545_O

2 i1_mult_4/smult_booth_rip1/u348_O

2 i1_mult_4/smult_booth_rip1/u341_O

2 i1_mult_4/smult_booth_rip1/u339_O

2 i1_mult_4/smult_booth_rip1/u12_O

2 imult4_e1_2<1>

2 i1_mult_4/smult_booth_rip1/u412_O

2 i1_mult_4/smult_booth_rip1/u226_O

2 i1_sub_3_sub_s1<1>

3 i1_sub_3/sub_rip1/u24_O

2 i1_sub_3/sub_rip1/u19_O

2 i1_sub_3_sub_s1<5>

3 i1_sub_3_sub_s1<6>

2 i1_sub_3/sub_rip1/u43_O

3 isub3_e1_2<0>

Split Nets:

2 isub3_e1_2<10>

2 isub3_e1_2<9>

2 isub3_e1_2<7>

3 isub3_e1_2<6>

2 isub3_e1_2<5>

2 isub3_e1_2<4>

11 PAD_clk

8 i1_e_lms_final/add6_e1_1_en

6 i1_e_lms_final/sub3_e1_1_en

3 PAD_entree_7<7>

2 PAD_entree_7<6>

3 PAD_entree_7<5>

4 i1_e_lms_final/sortie_4_en

12 PAD_reset<0>

2 i1_e_lms_final/dly5_s<10>

2 i1_e_lms_final/dly5_s<8>

2 i1_e_lms_final/dly5_s<7>

2 i1_e_lms_final/dly5_s<6>

2 i1_e_lms_final/dly5_s<3>

2 i1_e_lms_final/dly5_s<0>

2 i1_e_lms_final/dly7_s<9>

2 i1_e_lms_final/dly7_s<8>

2 i1_e_lms_final/dly7_s<7>

2 i1_e_lms_final/dly7_s<6>

2 i1_e_lms_final/dly7_s<5>

2 i1_e_lms_final/dly7_s<2>

2 i1_e_lms_final/dly7_s<1>

4 i1_e_lms_final/dly9_s<11>

3 i1_e_lms_final/dly9_s<10>

Split Nets:

3 i1_e_lms_final/dly9_s<9>

2 i1_e_lms_final/dly9_s<8>

3 i1_e_lms_final/dly9_s<7>

5 i1_e_lms_final/dly9_s<6>

3 i1_e_lms_final/dly9_s<5>

2 i1_e_lms_final/dly9_s<3>

2 i1_e_lms_final/dly11_s<11>

3 i1_e_lms_final/dly11_s<9>

2 i1_e_lms_final/dly11_s<1>

24 i1_e_lms_final/dly7_s_en

2 i1_e_lms_final/dly51_s<8>

3 i1_e_lms_final/dly51_s<7>

2 i1_e_lms_final/dly51_s<5>

2 i1_e_lms_final/dly51_s<4>

3 i1_e_lms_final/dly51_s<3>

2 i1_e_lms_final/dly51_s<2>

3 i1_e_lms_final/dly51_s<1>

17 i1_e_lms_final/dly5_s_en

2 i1_e_lms_final/dly50_s<9>

2 i1_e_lms_final/dly50_s<7>

2 i1_e_lms_final/dly49_s<2>

15 i1_e_lms_final/c_step_n<2>

2 i1_e_lms_final/dly47_s<11>

3 i1_e_lms_final/dly47_s<0>

5 i1_e_lms_final/c_step<2>

2 i1_e_lms_final/dly46_s<5>

2 i1_e_lms_final/dly45_s<11>

2 i1_e_lms_final/dly45_s<9>

Split Nets:

2 i1_e_lms_final/dly45_s<6>

2 i1_e_lms_final/dly43_s<11>

2 i1_e_lms_final/dly43_s<3>

2 i1_e_lms_final/dly41_s<11>

2 i1_e_lms_final/dly41_s<8>

2 i1_e_lms_final/dly41_s<5>

2 i1_e_lms_final/dly41_s<4>

2 i1_e_lms_final/dly39_s<9>

2 i1_e_lms_final/dly39_s<8>

2 i1_e_lms_final/dly37_s<11>

2 i1_e_lms_final/dly37_s<5>

2 i1_e_lms_final/dly37_s<4>

3 i1_e_lms_final/dly37_s<2>

2 i1_e_lms_final/dly37_s<1>

2 i1_e_lms_final/dly25_s<6>

2 i1_e_lms_final/dly25_s<1>

2 i1_e_lms_final/dly22_s<9>

2 i1_e_lms_final/dly22_s<6>

2 i1_e_lms_final/dly22_s<1>

2 i1_e_lms_final/dly22_s<0>

2 i1_e_lms_final/dly20_s<8>

3 i1_e_lms_final/dly20_s<6>

2 i1_e_lms_final/dly20_s<4>

2 i1_e_lms_final/dly20_s<3>

3 i1_e_lms_final/dly20_s<2>

3 i1_e_lms_final/dly17_s<8>

2 i1_e_lms_final/dly17_s<3>

2 i1_e_lms_final/dly15_s<9>

2 i1_e_lms_final/dly15_s<7>

Split Nets:

2 i1_e_lms_final/dly15_s<6>

2 i1_e_lms_final/dly15_s<3>

2 i1_e_lms_final/c_step<1>

13 i1_e_lms_final/c_step<0>

3 PAD_entree_2<1>

2 PAD_entree_2<2>

2 PAD_entree_1<4>

2 PAD_entree_2<5>

2 PAD_entree_4<5>

2 PAD_entree_1<7>

4 PAD_entree_5<0>

4 i1_e_lms_final/u324_O

3 PAD_entree_5<1>

2 PAD_entree_6<1>

3 PAD_entree_5<2>

2 PAD_entree_5<4>

2 PAD_entree_6<4>

3 PAD_entree_5<5>

2 PAD_entree_6<6>

13 i1_e_lms_final/u7_O

Information in Other Reports

----------------------------

Since not all pertinent design information is listed in this PPR

report file, this section describes where additional information can

be found.

Information Report File Created By

----------------------------------------- ----------- ----------

Connection of signals between levels of design.mrg XNFMERGE

design hierarchy

Resolution of relative location (RLOC) design.mrg XNFMERGE

constraints through design hierarchy

X-BLOX designs: design rule check for design.prx XNFPREP

pre-expanded design

X-BLOX designs: results of optimization design.blx XBLOX

and module expansion in X-BLOX

Design rule check for invalid and/or design.prp XNFPREP

inefficient use of LCA architecture

Unused or disabled logic removed from design.prp XNFPREP

design, due to sourceless or loadless

signals and VCC or ground connections

XC3000A/L designs: Mapping of design design.crf XNFMAP

logic into each CLB or IOB

XC3000A/L designs: Summary of guided design.crf XNFMAP

partitioning results

========== End of Report ==========