-------------------------------------------------------------------------------
-- Project : DSP21020
-- Laboratory : SEI/IRESTE
-- File name : RF.vhd
-- Title : DSP21020_RF Entity/Architecture
-- Description : Register File
-- Design Library : LIB_DSP
-- Analysis Dependency : No
-- Initialization : No
-- Notes : non synthesizable model
-- Simulator : Model Technology
-------------------------------------------------------------------------------
-- Revisions :
-- Date Author Revision Comments
-- 20/01/96 F. Bouchard 0.1 Creation - decoding
-- 09/02/96 0.2 added ram
-------------------------------------------------------------------------------
library Util_Pkgs;
use Util_Pkgs.DSP21020_pkg.all;
entity DSP21020_RF_Nty is -- entity decl. for the Register File
port(
CK : in bit;
HLDB : in bit;
RST : in bit;
ABORT : in bit;
WRDRV : in bit;
NCEN : in bit;
I : in BV48_Typ;
IDMD : inout BV40R_Typ; -- the DMD bus
IPMD : inout BV48R_Typ; -- the PMD bus
PS_COMPD1F : in bit; -- from Main decoder
PS_T6D1F : in bit; -- type 6 instr, from Main decoder
PS_DTEXD1F : in BV4_Typ; -- in type 6 instr, from Main decoder
PS_SRRFH1F : in bit; -- MODE1 reg, bit 7. Shadow reg sel
PS_SRRFL1F : in bit; -- MODE1 reg, bit 10. Shadow reg sel
PS_DMRDD1F : in bit; -- read from data mem. Write to RF
PS_DMWRD1F : in bit; -- Write to data mem. read from RF
PS_PMRDD1F : in bit; -- read from prog mem. Write to RF
PS_PMWRD1F : in bit; -- Write to prog mem. read from RF
PS_DMREGD1F : in BV4_Typ; -- RF's data mem addr.
-- Source for ureg <- ureg
PS_PMREGD1F : in BV4_Typ; -- RF's prog mem addr.
-- Dest. for ureg <- ureg
SY_DMDOUTE1F : in bit; -- Enable DXCVR output (to RF)
SY_DMREADY2F : in bit;
SY_PMREADY2F : in bit;
AR2F : in BV40_Typ; -- The ALU's result bus
SR2F : in BV40_Typ; -- The shifters result bus
--(doubles as ALU's subtraction
-- result bus for dual add/sub-
-- tract operations
MFR2F : in BV40_Typ; -- The multiplier's result bus
ASX2F : out BV40_Typ; -- The ALU's (and Shifter's) x-operand
ASY2F : out BV40_Typ; -- The ALU's (and Shifter's) y-operand
MFX2F : out BV40_Typ; -- The Multiplier's x-operand
MFY2F : out BV40_Typ; -- The Multiplier's y-operand
ASZ2F : out BV32_Typ; -- The Shifter's third input operand
RF_ALSD2F : inout bit; -- to ALU, prog seq, mem interface
RF_SHSD2F : inout bit; -- to shifter, prog seq
RF_MUSD2F : inout bit; -- to MULT
RF_MULD2F : inout bit; -- not a xfer instr,to prog seq,
-- mem interface
RF_T5D2F : out bit; -- type 5 instr, to MULT
RF_CACCUD2F : out bit; -- ALU compare instr, to prog seq
RF_ASOPD2F : out BV8_Typ; -- to ALU, shifter
RF_MFOPD2F : out BV8_Typ; -- to MULT
IMSHF0F : out bit; -- to RF DataPath
IMSHFD : out BV12_Typ -- imm shift data, to RF DataPath
);
end DSP21020_RF_Nty;
architecture RF_Algo1 of DSP21020_RF_Nty is
signal PHI1, PHI2 : bit;
begin
RFproc: process (PHI1, PHI2)
variable IL_v : BV48_Typ;
constant NoCompute : bit_vector (10 downto 0) := "00000000000";
variable Asop_v : BV3_Typ := "000";
variable Mfop_v : BV3_Typ := "000";
variable Srrfh2f_v, Srrfl2f_v, Srrfh1f_v, Srrfl1f_v : bit;
variable R_v : RFram_Typ;-- := (8=>X"000000000C", others=>X"0000000000");
variable RX1ADRD2F_v, RY1ADRD2F_v, RX2ADRD2F_v, RY2ADRD2F_v : BV4_Typ;
variable RN1ADRD2F_v, RN2ADRD2F_v, RN3ADRD2F_v : BV4_Typ;
variable RDRX1D2F_v, RDRX2D2F_v, RDRY1D2F_v, RDRY2D2F_v, RDRN1D2F_v : bit;
variable WRRN1D2F_v, WRRN2D2F_v, WRRN3D2F_v : bit;
variable RX1Adr_v, RX2Adr_v, RY1Adr_v, RY2Adr_v : natural;
variable RN1Adr_v, RN2Adr_v, RN3Adr_v : natural;
variable WrRN1_v, WrRN2_v, WrRN3_v : bit;
variable RFAlsd2f_v, RFShsd2f_v, RFMuld2f_v : bit;
variable RFals_v, RFshs_v, RFmul_v : bit;
variable DrvDmdd2f_v, RdDmdd2f_v : bit;
variable DrvPmdd2f_v, RdPmdd2f_v : bit;
variable DmRdAdrd2f_v, DmWrAdrd2f_v, PmRdAdrd2f_v, PmWrAdrd2f_v : BV4_Typ;
variable RdDmde1f_v, RdPmde1f_v : bit;
variable DmRdAdr_v, PmRdAdr_v, DmWrAdr_v, PmWrAdr_v : natural;
variable DRVDMD1F_v, DRVPMD1F_v : bit;
variable DMDOUTE1F_v : bit;
begin
if ((SY_DMDOUTE1F='1') and (WRDRV='1')) then
DMDOUTE1F_v := '1';
else
DMDOUTE1F_v := '0';
end if;
if (PHI1='1') then
IL_v := I; -- D1
if (ABORT='0') then -- begin E1
WrRN1_v := WRRN1D2F_v;
WrRN2_v := WRRN2D2F_v;
WrRN3_v := WRRN3D2F_v;
else
WrRN1_v := '0';
WrRN2_v := '0';
WrRN3_v := '0';
end if;
RN1Adr_v := Bin2Nat(RN1ADRD2F_v);
RN2Adr_v := Bin2Nat(RN2ADRD2F_v);
RN3Adr_v := Bin2Nat(RN3ADRD2F_v);
RFals_v := RFAlsd2f_v;
RFshs_v := RFShsd2f_v;
RFmul_v := RFMuld2f_v;
Srrfh1f_v := Srrfh2f_v;
Srrfl1f_v := Srrfl2f_v;
DmRdAdr_v := Bin2Nat(DmRdAdrd2f_v);
PmRdAdr_v := Bin2Nat(PmRdAdrd2f_v);
if (not((ABORT='1') or (RST='1')) and (WRDRV='1')) then
DRVDMD1F_v := DrvDmdd2f_v;
else
DRVDMD1F_v := '0';
end if;
if (not((ABORT='1') or (RST='1')) and (WRDRV='1')) then
DRVPMD1F_v := DrvPmdd2f_v;
else
DRVPMD1F_v := '0';
end if;
if (DRVDMD1F_v='0') and (DMDOUTE1F_v='1') then
IDMD(7 downto 0) <= X"00";
elsif ((DRVDMD1F_v='1') and (DMDOUTE1F_v='0')) then
if (((Srrfl2f_v='0') and (DmRdAdr_v < 8)) or
((Srrfh2f_v='0') and (DmRdAdr_v >= 8))) then
IDMD <= To_Bit_Vector_Res(R_v(DmRdAdr_v));
else -- shadow reg selected
IDMD <= To_Bit_Vector_Res(R_v(16+DmRdAdr_v));
end if;
end if;
if (DRVPMD1F_v='1') then
IPMD(7 downto 0) <= X"00";
if (((Srrfl2f_v='0') and (PmRdAdr_v < 8)) or
((Srrfh2f_v='0') and (PmRdAdr_v >= 8))) then
IPMD(47 downto 8) <= To_Bit_Vector_Res(R_v(PmRdAdr_v));
else
IPMD(47 downto 8) <= To_Bit_Vector_Res(R_v(16+PmRdAdr_v));
end if;
end if;
RdDmde1f_v := RdDmdd2f_v;
RdPmde1f_v := RdPmdd2f_v;
DmWrAdr_v := Bin2Nat(DmWrAdrd2f_v);
PmWrAdr_v := Bin2Nat(PmWrAdrd2f_v); -- end E1
end if;
if (PHI2='1') then
if (WrRN1_v='1') then -- write reg on E2
if (RFals_v='1') then
if (((Srrfl1f_v='0') and (RN1Adr_v < 8)) or
((Srrfh1f_v='0') and (RN1Adr_v >= 8))) then
R_v(RN1Adr_v) := AR2F;
else -- shadow reg selected
R_v(16+RN1Adr_v) := AR2F;
end if;
elsif (RFmul_v='1') then
if (((Srrfl1f_v='0') and (RN1Adr_v < 8)) or
((Srrfh1f_v='0') and (RN1Adr_v >= 8))) then
R_v(RN1Adr_v) := MFR2F;
else -- shadow reg selected
R_v(16+RN1Adr_v) := MFR2F;
end if;
elsif (RFshs_v='1') then
if (((Srrfl1f_v='0') and (RN1Adr_v < 8)) or
((Srrfh1f_v='0') and (RN1Adr_v >= 8))) then
R_v(RN1Adr_v) := SR2F;
else -- shadow reg selected
R_v(16+RN1Adr_v) := SR2F;
end if;
end if; -- ALU, mult, shift
end if; -- WrRN1_v
if (WrRN2_v='1') then
if ((RFals_v='1') and (RFmul_v='0') and (RFshs_v='0')) then
if (((Srrfl1f_v='0') and (RN2Adr_v < 8)) or
((Srrfh1f_v='0') and (RN2Adr_v >= 8))) then
R_v(RN2Adr_v) := SR2F;
else -- shadow reg selected
R_v(16+RN2Adr_v) := SR2F;
end if;
elsif ((RFals_v='1') and (RFmul_v='1')) then
if (((Srrfl1f_v='0') and (RN2Adr_v < 8)) or
((Srrfh1f_v='0') and (RN2Adr_v >= 8))) then
R_v(RN2Adr_v) := MFR2F;
else -- shadow reg selected
R_v(16+RN2Adr_v) := MFR2F;
end if;
end if; -- ALU, mult, shift
end if; -- WrRN2_v
if ((WrRN3_v='1') and (RFals_v='1') and (RFmul_v='1')) then
if (((Srrfl1f_v='0') and (RN3Adr_v < 8)) or
((Srrfh1f_v='0') and (RN3Adr_v >= 8))) then
R_v(RN3Adr_v) := SR2F;
else -- shadow reg selected
R_v(16+RN3Adr_v) := SR2F;
end if;
end if; -- WrRN3_v
if ((NCEN='1') and (SY_DMREADY2F='1')) then
if (RdDmde1f_v='1') then
if (((Srrfl1f_v='0') and (DmWrAdr_v < 8)) or
((Srrfh1f_v='0') and (DmWrAdr_v >= 8))) then
R_v(DmWrAdr_v) := To_bit_vector(IDMD);
else -- shadow reg selected
R_v(16+DmWrAdr_v) := To_bit_vector(IDMD);
end if;
end if;
if (RdPmde1f_v='1') then
if (((Srrfl1f_v='0') and (PmWrAdr_v < 8)) or
((Srrfh1f_v='0') and (PmWrAdr_v >= 8))) then
R_v(PmWrAdr_v) := To_bit_vector(IPMD(47 downto 8));
else -- shadow reg selected
R_v(16+PmWrAdr_v) := To_bit_vector(IPMD(47 downto 8));
end if;
end if;
end if; -- end E2
-- COMPUTE instruction -- begin D2
if (PS_COMPD1F = '1') then
-- type 0
if (IL_v(22 downto 12) = NoCompute) then
RF_ALSD2F <= '0';
RFAlsd2f_v := '0';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '0';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_ASOPD2F <= X"00";
RF_MFOPD2F <= X"00";
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
RX1ADRD2F_v := X"0";
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := X"0";
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := X"0";
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '0';
RDRX2D2F_v := '0';
RDRY1D2F_v := '0';
RDRY2D2F_v := '0';
RDRN1D2F_v := '0';
WRRN1D2F_v := '0';
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
-- type I (ALU)
elsif ((IL_v(22 downto 20) = "000") and
(IL_v(19 downto 12) /= X"00") and
(IL_v(18 downto 16) /= "111")) then
RF_ALSD2F <= '1';
RFAlsd2f_v := '1';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '0';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_ASOPD2F <= IL_v(19 downto 12);
RF_MFOPD2F <= X"00";
RF_T5D2F <= '0';
if ((IL_v(19 downto 12) = X"0A") or (IL_v(19 downto 12) = X"8A")) then
RF_CACCUD2F <= '1'; -- COMP(Rx,Ry). Don't write back to RF
else
RF_CACCUD2F <= '0';
end if;
IMSHF0F <= '0';
RX1ADRD2F_v := IL_v(7 downto 4);
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := IL_v(3 downto 0);
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := IL_v(11 downto 8);
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '1';
RDRX2D2F_v := '0';
RDRY1D2F_v := '1';
RDRY2D2F_v := '0';
RDRN1D2F_v := '0';
if ((IL_v(19 downto 12) = X"0A") or (IL_v(19 downto 12) = X"8A")) then
WRRN1D2F_v := '0'; -- COMP(Rx,Ry). Don't write back to RF
else
WRRN1D2F_v := '1';
end if;
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
-- type I (multiplier)
elsif (IL_v(22 downto 20) = "001") then
RF_ALSD2F <= '0';
RFAlsd2f_v := '0';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '1';
RF_MULD2F <= '1';
RFMuld2f_v := '1';
RF_ASOPD2F <= X"00";
RF_MFOPD2F <= IL_v(19 downto 12);
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
RX1ADRD2F_v := IL_v(7 downto 4);
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := IL_v(3 downto 0);
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := IL_v(11 downto 8);
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '1';
RDRX2D2F_v := '0';
RDRY1D2F_v := '1';
RDRY2D2F_v := '0';
RDRN1D2F_v := '0';
if (IL_v(14) = '1') then -- Accumulate. Don't write back to RF
WRRN1D2F_v := '0';
else
WRRN1D2F_v := '1';
end if;
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
-- type I (shifter)
elsif (IL_v(22 downto 20) = "010") then
RF_ALSD2F <= '0';
RFAlsd2f_v := '0';
RF_SHSD2F <= '1';
RFShsd2f_v := '1';
RF_MUSD2F <= '0';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_ASOPD2F <= IL_v(19 downto 12);
RF_MFOPD2F <= X"00";
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
RX1ADRD2F_v := IL_v(7 downto 4);
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := IL_v(3 downto 0);
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := IL_v(11 downto 8);
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '1';
RDRX2D2F_v := '0';
RDRY1D2F_v := '1';
RDRY2D2F_v := '0';
RDRN1D2F_v := '1';
if (IL_v(19 downto 12) = X"CC") then
WRRN1D2F_v := '0'; -- BTST Rx BY Ry. Don't write back to RF
else
WRRN1D2F_v := '1';
end if;
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
-- type II (dual add/subtract)
elsif ((IL_v(22 downto 20) = "000") and
(IL_v(18 downto 16) = "111")) then
RF_ALSD2F <= '1';
RFAlsd2f_v := '1';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '0';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_ASOPD2F <= IL_v(19 downto 12);
RF_MFOPD2F <= X"00";
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
RX1ADRD2F_v := IL_v(7 downto 4);
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := IL_v(3 downto 0);
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := IL_v(11 downto 8); -- add result
RN2ADRD2F_v := IL_v(15 downto 12); -- sub result
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '1';
RDRX2D2F_v := '0';
RDRY1D2F_v := '1';
RDRY2D2F_v := '0';
RDRN1D2F_v := '0';
WRRN1D2F_v := '1';
WRRN2D2F_v := '1';
WRRN3D2F_v := '0';
-- type III (parallel multiplier and ALU)
elsif ((IL_v(22 downto 21) = "10") and
(IL_v(20 downto 17) /= "0000")) then
RF_ALSD2F <= '1';
RFAlsd2f_v := '1';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '1';
RF_MULD2F <= '1';
RFMuld2f_v := '1';
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
Asop_v := IL_v(18 downto 16);
Mfop_v := IL_v(20 downto 18);
case Mfop_v is
when "001" => RF_MFOPD2F <= X"79";
when "010" => RF_MFOPD2F <= X"BC";
when "011" => RF_MFOPD2F <= X"B9";
when "100" => RF_MFOPD2F <= X"FC";
when "101" => RF_MFOPD2F <= X"F9";
when "110" => RF_MFOPD2F <= X"30";
when "111" => RF_MFOPD2F <= X"30";
when others => RF_MFOPD2F <= X"00"; -- release
end case;
if (IL_v(20 downto 19) = "11") then -- floating-point
case Asop_v is
when "000" => RF_ASOPD2F <= X"81";
when "001" => RF_ASOPD2F <= X"82";
when "010" => RF_ASOPD2F <= X"DA";
when "011" => RF_ASOPD2F <= X"D9";
when "100" => RF_ASOPD2F <= X"89";
when "101" => RF_ASOPD2F <= X"B0";
when "110" => RF_ASOPD2F <= X"E2";
when "111" => RF_ASOPD2F <= X"E1";
when others => RF_ASOPD2F <= X"00"; -- error
end case;
else -- fixed-point
case Asop_v is
when "000" | "100" => RF_ASOPD2F <= X"01";
when "001" | "101" => RF_ASOPD2F <= X"02";
when "010" | "110" => RF_ASOPD2F <= X"09";
when "011" | "111" => RF_ASOPD2F <= X"00"; -- reserved opcode!
when others => RF_ASOPD2F <= X"00"; -- error
end case;
end if;
RX1ADRD2F_v := "10" & IL_v(3 downto 2); -- ALU
RX2ADRD2F_v := "00" & IL_v(7 downto 6); -- Mult
RY1ADRD2F_v := "11" & IL_v(1 downto 0); -- ALU
RY2ADRD2F_v := "01" & IL_v(5 downto 4); -- Mult
RN1ADRD2F_v := IL_v(11 downto 8); -- ALU
RN2ADRD2F_v := IL_v(15 downto 12); -- Mult
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '1';
RDRX2D2F_v := '1';
RDRY1D2F_v := '1';
RDRY2D2F_v := '1';
RDRN1D2F_v := '0';
WRRN1D2F_v := '1';
if ((Mfop_v = "010") or (Mfop_v = "100")) then
WRRN2D2F_v := '0'; -- Accumulate. Don't write back to RF
else
WRRN2D2F_v := '1';
end if;
WRRN3D2F_v := '0';
-- type IV (parallel multiplier and dual add/subtract)
elsif (IL_v(22 downto 21) = "11") then
RF_ALSD2F <= '1';
RFAlsd2f_v := '1';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '1';
RF_MULD2F <= '1';
RFMuld2f_v := '1';
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
if (IL_v(20) = '0') then -- fixed-point
RF_ASOPD2F <= X"70";
RF_MFOPD2F <= X"79";
else -- floating-point
RF_ASOPD2F <= X"F0";
RF_MFOPD2F <= X"30";
end if;
RX1ADRD2F_v := "10" & IL_v(3 downto 2); -- ALU
RX2ADRD2F_v := "00" & IL_v(7 downto 6); -- Mult
RY1ADRD2F_v := "11" & IL_v(1 downto 0); -- ALU
RY2ADRD2F_v := "01" & IL_v(5 downto 4); -- Mult
RN1ADRD2F_v := IL_v(11 downto 8); -- add result
RN2ADRD2F_v := IL_v(15 downto 12); -- mult result
RN3ADRD2F_v := IL_v(19 downto 16); -- sub result
RDRX1D2F_v := '1';
RDRX2D2F_v := '1';
RDRY1D2F_v := '1';
RDRY2D2F_v := '1';
RDRN1D2F_v := '0';
WRRN1D2F_v := '1';
WRRN2D2F_v := '1';
WRRN3D2F_v := '1';
-- type V (RF <- MFR: multiplier)
elsif ((IL_v(22 downto 17) = "100000") and
(IL_v(16 downto 15) = "00")) then
RF_ALSD2F <= '0';
RFAlsd2f_v := '0';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '1';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_T5D2F <= '1';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
RX1ADRD2F_v := X"0";
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := X"0";
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := IL_v(11 downto 8);
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '0';
RDRX2D2F_v := '0';
RDRY1D2F_v := '0';
RDRY2D2F_v := '0';
RDRN1D2F_v := '0';
WRRN1D2F_v := '1';
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
RF_ASOPD2F <= X"00";
RF_MFOPD2F <= "000" & IL_v(16 downto 12);
-- type V (MFY <- RF: multiplier)
elsif ((IL_v(22 downto 17) = "100000") and
(IL_v(16 downto 15) = "10")) then
RF_ALSD2F <= '0';
RFAlsd2f_v := '0';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '1';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_T5D2F <= '1';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
RX1ADRD2F_v := X"0";
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := X"0";
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := IL_v(11 downto 8);
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '0';
RDRX2D2F_v := '0';
RDRY1D2F_v := '0';
RDRY2D2F_v := '0';
RDRN1D2F_v := '1';
WRRN1D2F_v := '0';
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
RF_ASOPD2F <= X"00";
RF_MFOPD2F <= "000" & IL_v(16 downto 12);
end if; -- end of compute instructions, except T6
-- IMMEDIATE SHIFT instruction
elsif (PS_T6D1F = '1') then
RF_ALSD2F <= '0';
RFAlsd2f_v := '0';
RF_SHSD2F <= '1';
RFShsd2f_v := '1';
RF_MUSD2F <= '0';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '1';
RF_ASOPD2F <= IL_v(21 downto 16) & "00";
RF_MFOPD2F <= X"00";
RX1ADRD2F_v := IL_v(3 downto 0);
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := X"0";
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := IL_v(7 downto 4);
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '1';
RDRX2D2F_v := '0';
RDRY1D2F_v := '0';
RDRY2D2F_v := '0';
RDRN1D2F_v := '1';
if ((IL_v(21 downto 16) & "00") = X"CC") then
WRRN1D2F_v := '0'; -- BTST Rx BY Ry. Don't write back to RF
else
WRRN1D2F_v := '1';
end if;
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
-- Neither a compute nor immediate instruction
else
RF_ALSD2F <= '0';
RFAlsd2f_v := '0';
RF_SHSD2F <= '0';
RFShsd2f_v := '0';
RF_MUSD2F <= '0';
RF_MULD2F <= '0';
RFMuld2f_v := '0';
RF_ASOPD2F <= X"00";
RF_MFOPD2F <= X"00";
RF_T5D2F <= '0';
RF_CACCUD2F <= '0';
IMSHF0F <= '0';
RX1ADRD2F_v := X"0";
RX2ADRD2F_v := X"0";
RY1ADRD2F_v := X"0";
RY2ADRD2F_v := X"0";
RN1ADRD2F_v := X"0";
RN2ADRD2F_v := X"0";
RN3ADRD2F_v := X"0";
RDRX1D2F_v := '0';
RDRX2D2F_v := '0';
RDRY1D2F_v := '0';
RDRY2D2F_v := '0';
RDRN1D2F_v := '0';
WRRN1D2F_v := '0';
WRRN2D2F_v := '0';
WRRN3D2F_v := '0';
end if; -- end T6 and none instruction
if ((PS_DMRDD1F='1') or (PS_DMWRD1F='1') or
(PS_PMRDD1F='1') or (PS_PMWRD1F='1')) then -- mem access instr
if ((PS_DMRDD1F='1') and (PS_DMWRD1F='0') and
(PS_PMRDD1F='0') and (PS_PMWRD1F='0')) then
DrvDmdd2f_v := '0';
RdDmdd2f_v := '1';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '0';
DmWrAdrd2f_v := PS_DMREGD1F;
elsif ((PS_DMRDD1F='1') and (PS_DMWRD1F='0') and
(PS_PMRDD1F='1') and (PS_PMWRD1F='0')) then
DrvDmdd2f_v := '0';
RdDmdd2f_v := '1';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '1';
DmWrAdrd2f_v := PS_DMREGD1F;
PmWrAdrd2f_v := PS_PMREGD1F;
elsif ((PS_DMRDD1F='1') and (PS_DMWRD1F='0') and
(PS_PMRDD1F='0') and (PS_PMWRD1F='1')) then
DrvDmdd2f_v := '0';
RdDmdd2f_v := '1';
DrvPmdd2f_v := '1';
RdPmdd2f_v := '0';
DmWrAdrd2f_v := PS_DMREGD1F;
PmRdAdrd2f_v := PS_PMREGD1F;
elsif ((PS_DMRDD1F='0') and (PS_DMWRD1F='1') and
(PS_PMRDD1F='0') and (PS_PMWRD1F='0')) then
DrvDmdd2f_v := '1';
RdDmdd2f_v := '0';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '0';
DmRdAdrd2f_v := PS_DMREGD1F;
elsif ((PS_DMRDD1F='0') and (PS_DMWRD1F='1') and
(PS_PMRDD1F='1') and (PS_PMWRD1F='0')) then
DrvDmdd2f_v := '1';
RdDmdd2f_v := '0';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '1';
DmRdAdrd2f_v := PS_DMREGD1F;
PmWrAdrd2f_v := PS_PMREGD1F;
elsif ((PS_DMRDD1F='0') and (PS_DMWRD1F='1') and
(PS_PMRDD1F='0') and (PS_PMWRD1F='1')) then
DrvDmdd2f_v := '1';
RdDmdd2f_v := '0';
DrvPmdd2f_v := '1';
RdPmdd2f_v := '0';
DmRdAdrd2f_v := PS_DMREGD1F;
PmRdAdrd2f_v := PS_PMREGD1F;
elsif ((PS_DMRDD1F='0') and (PS_DMWRD1F='0') and
(PS_PMRDD1F='1') and (PS_PMWRD1F='0')) then
DrvDmdd2f_v := '0';
RdDmdd2f_v := '0';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '1';
PmWrAdrd2f_v := PS_PMREGD1F;
elsif ((PS_DMRDD1F='0') and (PS_DMWRD1F='0') and
(PS_PMRDD1F='0') and (PS_PMWRD1F='1')) then
DrvDmdd2f_v := '0';
RdDmdd2f_v := '0';
DrvPmdd2f_v := '1';
RdPmdd2f_v := '0';
PmRdAdrd2f_v := PS_PMREGD1F;
elsif ((PS_DMRDD1F='1') and (PS_DMWRD1F='1') and
(PS_PMRDD1F='0') and (PS_PMWRD1F='0')) then
DrvDmdd2f_v := '1';
RdDmdd2f_v := '1';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '0';
DmRdAdrd2f_v := PS_DMREGD1F;
DmWrAdrd2f_v := PS_PMREGD1F;
else
DrvDmdd2f_v := '0';
RdDmdd2f_v := '0';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '0';
end if;
else
DrvDmdd2f_v := '0';
RdDmdd2f_v := '0';
DrvPmdd2f_v := '0';
RdPmdd2f_v := '0';
end if; -- mem access instr
-- for immediate shift
IMSHFD(11 downto 8) <= PS_DTEXD1F;
IMSHFD(7 downto 0) <= IL_v(15 downto 8);
Srrfh2f_v := PS_SRRFH1F;
Srrfl2f_v := PS_SRRFL1F;
if (RDRX1D2F_v='1') then
RX1Adr_v := Bin2Nat(RX1ADRD2F_v);
if ((RFAlsd2f_v='1') or (RFShsd2f_v='1')) then
if (((Srrfl2f_v='0') and (RX1Adr_v < 8)) or
((Srrfh2f_v='0') and (RX1Adr_v >= 8))) then
ASX2F <= R_v(RX1Adr_v);
else -- shadow reg selected
ASX2F <= R_v(16+RX1Adr_v);
end if;
elsif (RFMuld2f_v='1') then
if (((Srrfl2f_v='0') and (RX1Adr_v < 8)) or
((Srrfh2f_v='0') and (RX1Adr_v >= 8))) then
MFX2F <= R_v(RX1Adr_v);
else -- shadow reg selected
MFX2F <= R_v(16+RX1Adr_v);
end if;
end if; -- ALU, shift or mult
end if; -- RDRX1D2F_v
if (RDRY1D2F_v='1') then
RY1Adr_v := Bin2Nat(RY1ADRD2F_v);
if ((RFAlsd2f_v='1') or ((RFShsd2f_v='1') and (PS_T6D1F='0'))) then
if (((Srrfl2f_v='0') and (RY1Adr_v < 8)) or
((Srrfh2f_v='0') and (RY1Adr_v >= 8))) then
ASY2F <= R_v(RY1Adr_v);
else -- shadow reg selected
ASY2F <= R_v(16+RY1Adr_v);
end if;
elsif (RFMuld2f_v='1') then
if (((Srrfl2f_v='0') and (RY1Adr_v < 8)) or
((Srrfh2f_v='0') and (RY1Adr_v >= 8))) then
MFY2F <= R_v(RY1Adr_v);
else -- shadow reg selected
MFY2F <= R_v(16+RY1Adr_v);
end if;
end if; -- ALU, shift or mult
end if; -- RDRY1D2F_v
if (RDRN1D2F_v='1') then
RN1Adr_v := Bin2Nat(RN1ADRD2F_v);
if (RFShsd2f_v='1') then
if (((Srrfl2f_v='0') and (RN1Adr_v < 8)) or
((Srrfh2f_v='0') and (RN1Adr_v >= 8))) then
ASZ2F <= R_v(RN1Adr_v)(39 downto 8);
else -- shadow reg selected
ASZ2F <= R_v(16+RN1Adr_v)(39 downto 8);
end if;
end if; -- shift
end if; -- RDRN1D2F_v
if ((RDRX2D2F_v='1') and (RFAlsd2f_v='1') and (RFMuld2f_v='1')) then
RX2Adr_v := Bin2Nat(RX2ADRD2F_v);
if (((Srrfl2f_v='0') and (RX2Adr_v < 8)) or
((Srrfh2f_v='0') and (RX2Adr_v >= 8))) then
MFX2F <= R_v(RX2Adr_v);
else -- shadow reg selected
MFX2F <= R_v(16+RX2Adr_v);
end if;
end if; -- RDRX2D2F_v
if ((RDRY2D2F_v='1') and (RFAlsd2f_v='1') and (RFMuld2f_v='1')) then
RY2Adr_v := Bin2Nat(RY2ADRD2F_v);
if (((Srrfl2f_v='0') and (RY2Adr_v < 8)) or
((Srrfh2f_v='0') and (RY2Adr_v >= 8))) then
MFY2F <= R_v(RY2Adr_v);
else -- shadow reg selected
MFY2F <= R_v(16+RY2Adr_v);
end if;
end if; -- RDRY2D2F_v -- end D2
IDMD <= X"0000000000";
IPMD <= X"000000000000";
end if; -- end PHI2
end process RFproc;
Clock: process (CK)
begin
if ((CK='1') and (HLDB='1')) then
PHI1 <= '1';
else
PHI1 <= '0';
end if;
if ((CK='0') or (HLDB='0')) then
PHI2 <= '1';
else
PHI2 <= '0';
end if;
end process Clock;
end RF_Algo1;