architecture SIMPLE_IO of vREG is
signal d: BIT_VECTOR(1 to 8);
signal s,pe,ne:BIT;
component REGISTRE 
port(di: in BIT_VECTOR(1 to 8); strb: in BIT;
     ds1,nds2: in BIT; do: out BIT_VECTOR(1 to 8));
end component ;
for iR: REGISTRE
  use entity work.REGISTRE(SIMPLE_IO_TIMING);

begin
  iR: REGISTRE
  port map(d,s,pe,ne,open);
process
  begin
  d<="10101010","11110000" after 30ns, "00001111" after 70ns, 
     "10110100" after 125ns, "01000111" after 180ns; 
  s<='1' after 20ns,'0' after 50ns, '1' after 80ns;
  ne<='1' after 50ns, '0' after 80ns,'1' after 100ns ;
  pe<='1' after 10ns, '0' after 120ns,'1' after 150ns;
  wait;
end process;
end SIMPLE_IO;


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