-- second implementation
architecture SIMPLE_IO_TIMING of REGISTRE is
signal reg: BIT_VECTOR(1 to 8);
constant strb_del:TIME:=40ns;
constant odel:TIME:=60ns;
constant en_del:TIME:=20ns;
begin
  SIMPLE:process(strb,ds1,nds2)
  begin
    if strb='1' and not strb'stable then
      reg <= di after strb_del ;
      if ds1='1' and nds2='0' then
	do <= di after strb_del+odel;
      else
	do <= "11111111" after strb_del+odel;
      end if;
    elsif not ds1'stable or not nds2'stable then
      if ds1='1' and nds2='0' then
	do <= reg after en_del+odel;
      else
	do <= "11111111" after en_del+odel;
      end if;
    end if;
  end process SIMPLE;
end SIMPLE_IO_TIMING; 


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