----------------------------------------------------------------------------------
--  Antonio E COSTA						Jerome CAZIN	--
--				SEII3 - Decembre 96				--
--										--
--	Entite Controle Sortie,entite qui gere la repartition des cellules	--
--			vers les buffers en sortie.				--
----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
--				Contrôle Sorties				--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity CTRL_SORTIES is
   port(  RESETB	:in std_logic;
	  CLK		:in std_logic;
	  SORTIE_DONNEE :in std_logic_vector(63 downto 0);
	  WREN		:in std_logic;
	  VCI		:in std_logic_vector(15 downto 0);
	  BUS_SORTIE	:out std_logic_vector (63 downto 0);
	  consom	:out std_logic;
	  WRITE		:out std_logic_vector(3 downto 0);
	  prete		:in std_logic
	);

end CTRL_SORTIES;
------------------------------------------------------------------------------------
--				Definition de Contrôle Sorties			  --
------------------------------------------------------------------------------------


architecture CTRL_SORTIES_ARC of CTRL_SORTIES is
  type TYPE_ETAT is (Repos,ATTENTE,Ecriture);
  
begin

process (CLK,RESETB)
 variable  ETAT :TYPE_ETAT;
 variable  VCIT :std_logic_vector (15 downto 0); 
  
begin
  if RESETB = '1' then ETAT:=Repos;
     VCIT := (others =>'0');
     consom <='0';
     WRITE <= (others =>'0');
     BUS_SORTIE <= (others => '0');
     
  elsif RISING_EDGE(clk) then
     case ETAT is
	when Repos =>
		if prete = '1' then
		ETAT:=ATTENTE;
		VCIT:=VCI;
		BUS_SORTIE<=SORTIE_DONNEE;
		consom <='1';
		end if;

	when ATTENTE=>
		case VCIT (4 downto 0) is
		 when "00001"=> WRITE(0) <='1';
		 when "00010"=> WRITE(1) <='1';
		 when "00011"=> WRITE(2) <='1';
		 when "00100"=> WRITE(3) <='1';
		 when others => ETAT:=Ecriture;
		end case;
		
		if WREN = '1' and PRETE='0' then
		ETAT:=Ecriture;
		consom<='0';
		end if;
	when Ecriture =>
		WRITE<=(others => '0');
		if PRETE='1' and WREN = 'L' then
		ETAT:=ATTENTE;
		VCIT:=VCI;
		BUS_SORTIE<=SORTIE_DONNEE;
		consom<='1';
		end if;
	when others => ETAT:=Repos;
	end case;
  end if;
end process;
end CTRL_SORTIES_ARC;

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