----------------------------------------------------------------------------------
--  Antonio E COSTA						Jerome CAZIN	--
--				SEII3 - Decembre 96				--
--										--
--		Entite commutateur : basee sur l'architecture buffers en sortie	--
--		       		     avec 4 entrees / 4 sorties			--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

package UTILI is
type IOCELL is array (3 downto 0) of std_logic_vector(63 downto 0);
end UTILI;

library IEEE;
use IEEE.std_logic_1164.all;

library COMPASS_LIB;
use COMPASS_LIB.COMPASS.ALL;
use COMPASS_LIB.STDCOMP.all;
use WORK.UTILI.all;

-----------------------------------------------------------------------------------
--				Coeur du commutateur		      		 --
-----------------------------------------------------------------------------------

entity COMMUTATEUR is
	port (
		CLK		:in std_logic;
		RESETB		:in std_logic;
		E_Cellule 	:in IOCELL;
		S_Cellule	:out IOCELL;
		WRITEGENE	:in std_logic_vector(3 downto 0);
		READCONSOM	:in std_logic_vector(3 downto 0);
		WRENGENE	:out std_logic_vector(3 downto 0);
		RDENCONSOM	:out std_logic_vector(3 downto 0)
	      );
end COMMUTATEUR;

------------------------------------------------------------------------------------
--				Definition du coeur du commutateur		  --
------------------------------------------------------------------------------------

architecture COMMUTATEUR_ARC of COMMUTATEUR is

-- Declarartion des composants utilises --

 component FIFO
 
   port(   RAZ		: in std_logic;
	   CLK		: in std_logic;
	   WRITE	: in std_logic;
	   DI		: in std_logic_vector(63 downto 0);
	   READ		: in std_logic;
	   DO		: out std_logic_vector(63 downto 0);
	   RDEN		: out std_logic;
	   WREN		: out std_logic
	);
 end component;
 
 component FIFO_out
 
   port(   RAZ		: in std_logic;
	   CLK		: in std_logic;
	   WRITE	: in std_logic;
	   DI		: in std_logic_vector(63 downto 0);
	   READ		: in std_logic;
	   DO		: out std_logic_vector(63 downto 0);
	   RDEN		: out std_logic;
	   WREN		: out std_logic
	);
 end component;
 

 component CTRL_ENTREES
   port(   RESETB	:in std_logic;
	   CLK		:in std_logic;
	   RDEN		:in std_logic;
	   ENTREE_DONNEE:in std_logic_vector (63 downto 0);
	   SORTIE_DONNEE:out std_logic_vector(63 downto 0);
	   READ		:out std_logic_vector(3 downto 0);
	   VCI		:out std_logic_vector(15 downto 0);
	   prete	:out std_logic;
	   consom	:inout std_logic
	  
	);
 end component;

 component CTRL_SORTIES 
   port(  RESETB	:in std_logic;
	  CLK		:in std_logic;
	  SORTIE_DONNEE :in std_logic_vector(63 downto 0);
	  WREN		:in std_logic;
	  VCI		:in std_logic_vector(15 downto 0);
	  BUS_SORTIE	:out std_logic_vector (63 downto 0);
	  consom	:out std_logic;
	  WRITE		:out std_logic_vector(3 downto 0);
	  prete		:inout std_logic
	);
 end component;

-- Declaration des signaux internes servant a l'interconnection des composants --

 signal RDEN 	  	: std_logic;
 signal WREN 	  	: std_logic;
 signal PRETE		: std_logic;
 signal CONSOM		: std_logic;
 signal READ 	  	: std_logic_vector (3 downto 0);
 signal WRITE	  	: std_logic_vector (3 downto 0);
 signal VCI		: std_logic_vector (15 downto 0);
 signal BUS_SORTIE	: std_logic_vector (63 downto 0);
 SIGNAl ENTREE		: IOCELL;
-- signal ENTREE_DONNEE 	: std_logic_vector (63 downto 0) bus;
 signal ENTREE_DONNEE 	: std_logic_vector (63 downto 0) ;
 signal SORTIE_DONNEE	: std_logic_vector (63 downto 0);
 
begin 
-------- Instanciation des BUFFER d'entrée --------------------------------------

instancBUFFin3:FIFO

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITEGENE(3),
		  DI	=> E_Cellule(3),
		  READ  => READ (3),
		  DO	=> ENTREE_DONNEE,
		  RDEN	=> RDEN,
		  WREN	=> WRENGENE (3)
		 );
		 
 instancBUFFin2:FIFO

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITEGENE(2),
		  DI	=> E_Cellule(2),
		  READ  => READ (2),
		  DO	=> ENTREE_DONNEE,
		  RDEN	=> RDEN,
		  WREN	=> WRENGENE (2)
		 );
instancBUFFin1:FIFO

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITEGENE(1),
		  DI	=> E_Cellule(1),
		  READ  => READ (1),
		  DO	=> ENTREE_DONNEE,
		  RDEN	=> RDEN,
		  WREN	=> WRENGENE (1)
		 );
		 
instancBUFFin0:FIFO

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITEGENE(0),
		  DI	=> E_Cellule(0),
		  READ  => READ (0),
		  DO	=> ENTREE_DONNEE,
		  RDEN	=> RDEN,
		  WREN	=> WRENGENE (0)
		 );

-------- Instanciation des BUFFER de sortie --------------------------------------
instancBUFFout3 :FIFO_out

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITE (3),
		  DI	=> BUS_SORTIE,
		  READ  => READCONSOM (3),
		  DO	=> S_Cellule(3),
		  RDEN	=> RDENCONSOM (3),
		  WREN	=> WREN
		 );
 
instancBUFFout2 :FIFO_out

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITE (2),
		  DI	=> BUS_SORTIE,
		  READ  => READCONSOM (2),
		  DO	=> S_Cellule(2),
		  RDEN	=> RDENCONSOM (2),
		  WREN	=> WREN
		 );
  

instancBUFFout1 :FIFO_out

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITE (1),
		  DI	=> BUS_SORTIE,
		  READ  => READCONSOM (1),
		  DO	=> S_Cellule(1),
		  RDEN	=> RDENCONSOM (1),
		  WREN	=> WREN
		 );
		 
instancBUFFout0 :FIFO_out

	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITE (0),
		  DI	=> BUS_SORTIE,
		  READ  => READCONSOM (0),
		  DO	=> S_Cellule(0),
		  RDEN	=> RDENCONSOM (0),
		  WREN	=> WREN
		 );
-------- Instanciation de Controle Entrée --------------------------------------
instancCTRL_ENTREES:CTRL_ENTREES
	port map (RESETB	=> RESETB,
		  CLK		=> CLK,
		  RDEN		=> RDEN,
		  ENTREE_DONNEE => ENTREE_DONNEE,
		  SORTIE_DONNEE	=> SORTIE_DONNEE,
		  READ		=> READ,
		  VCI		=> VCI,
		  PRETE		=> PRETE,
		  CONSOM	=> CONSOM
		);

-------- Instanciation de Controle Sorties --------------------------------------
instancCTRL_SORTIES:CTRL_SORTIES
	port map (RESETB	=> RESETB,
		  CLK		=> CLK,
		  SORTIE_DONNEE => SORTIE_DONNEE,
		  WREN		=> WREN,
		  VCI		=> VCI,
		  BUS_SORTIE	=> BUS_SORTIE,
		  CONSOM	=> CONSOM,
		  WRITE		=> WRITE,
		  PRETE		=> PRETE
		 );
end COMMUTATEUR_ARC;




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