---------------------------------------------------------------------------------- -- Antonio E COSTA Jerome CAZIN -- -- SEII3 - Decembre 96 -- -- -- -- TESTS : Ceci regroupe une fonction de test des buffers et un programme -- -- de test global, c'est a dire l' ensemble du commutateur plus un -- -- generateur de cellules et un consommateur de cellules -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ------------------------------ test du composant buffer -------------------------- entity TEST is end TEST; architecture TEST of TEST is constant NB:INTEGER:=3; constant NW:INTEGER:=7; subtype WORD is std_logic_vector(1 to NB); signal RESET : std_logic; signal WRITE : std_logic; signal CELLIN : WORD; signal READ : std_logic; signal CELLOUT : WORD; signal WREN : std_logic; signal RDEN : std_logic; signal CLK : std_logic; component FIFO generic (NB_BITS,NB_WORDS: INTEGER); port (RAZ,CLK,WRITE:in std_logic;DI:in WORD;READ:in std_logic; DO:out WORD;RDEN,WREN:out std_logic); end component; component HORLOGE_40M port (CLK :out std_logic); end component; begin inst : FIFO generic map (NB,NW) port map (RESET,clk,WRITE,CELLIN,READ,CELLOUT,RDEN,WREN); inst2: HORLOGE_40M port map(CLK); -- initialisations process begin reset <='1','0' after 25 ns; cellin <= "001" after 25 ns,"010" after 50 ns,"011" after 75 ns; write <='1' after 25 ns,'0' after 37 ns,'1' after 50 ns, '0' after 62 ns,'1' after 75 ns,'0' after 90 ns; read <='1' after 25 ns,'0' after 37 ns, '1' after 62 ns, '0' after 75 ns; wait; end process; end TEST; ------------------------------------------------------------------------------- -- Consommateur -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity CONSOMMATEUR is port( READ :out std_logic_vector(15 downto 0); RDEN :in std_logic_vector(15 downto 0) ); end CONSOMMATEUR; architecture CONSOMMATEUR_ARC of CONSOMMATEUR is type type_etat is (Debut_lecture,Fin_lecture); constant CYCLE_ACTIVATION : TIME :=13 ns; SIGNAL ETAT : type_etat:=Debut_lecture; begin process variable i : NATURAL:=0; variable N_WORD : NATURAL :=0; begin case etat is when Debut_lecture => read (i)<='1'; -- si l'on attendre que le commutateur reponde a la demande -- il suffit de supprimer les commanetaires --. -- Sinon le consommateur scrute toute les sorties sans attendre -- de reponse. On augmente ainsi le debit de sortie des cellules --if rden(i)='1' then ETAT<=Fin_lecture; --end if; when Fin_lecture => --if rden(i) = 'L' then --if n_word = 7 then --n_word:=0; read (i)<='0'; i:=i+1; if i=16 then i:=0;end if; ETAT<=Debut_lecture; --else --ETAT<=Debut_lecture; --N_WORD:=N_WORD+1; -- end if; --end if; when others => ETAT<=Debut_Lecture; end case; wait for CYCLE_ACTIVATION/2 ; end process; end CONSOMMATEUR_ARC; ------------------------------------------------------------------------------- -- Generateur de cellules -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.util.all; entity GENE_CEL is port ( WRITEGENE : out std_logic_vector(15 downto 0); WRENGENE : in std_logic_vector(15 downto 0); E_CELLULE : out std_logic_vector(63 downto 0) ); end GENE_CEL; architecture GENE_CEL_ARC of GENE_CEL is type type_etat is (Debut_Gene,Fin_Gene); constant CYCLE_ACTIVATION : TIME :=13 ns; begin process subtype NATURAL7 is NATURAL range 0 to 6; subtype NATURAL16 is NATURAL range 0 to 15; variable N_WORD : NATURAL7; variable N_ENTREE : NATURAL16:=0; variable ETAT : type_etat:=Debut_Gene; variable UNIFORME : REEL_UNIFORME; variable INIT : REEL_UNIFORME:=0.4; variable attente :Boolean :=FALSE; begin case etat is when Debut_Gene => UNIFORME := random (INIT); INIT:=UNIFORME; if uniforme > 0.5 or N_WORD>0 or attente then attente:=TRUE; WRITEGENE <= (others => '0'); WRITEGENE(N_entree)<='1'; E_CELLULE (27 downto 12) <=nat2bit(N_ENTREE+1+N_WORD); E_CELLULE (11 downto 0) <=(others =>'0'); E_CELLULE (63 downto 28) <= (others =>'0'); if WRENGENE(N_ENTREE)='1' then ETAT:=Fin_Gene; attente:=FALSE; end if; else WRITEGENE(N_entree)<='0'; if N_entree=15 then N_entree:=0; else N_entree:=N_entree+1; end if; ETAT:=Debut_Gene; end if; when Fin_Gene => WRITEGENE(N_entree)<='0'; if WRENGENE(N_entree) ='L' and N_word=6 then if N_entree=15 then N_entree:=0; else N_entree:=N_entree+1; end if; N_word:=0; ETAT:=Debut_Gene; elsif WRENGENE(N_entree)='L' then N_WORD:=N_WORD+1; ETAT:=Debut_Gene; end if; when others => ETAT:=Debut_Gene; end case; wait for CYCLE_ACTIVATION/2 ; end process; end Gene_Cel_ARC; -------------------------------------------------------- -- Test Global -- -------------------------------------------------------- library IEEE; USE IEEE.std_logic_1164.all; USE WORK.UTIL.all; entity test_global is port (CLK :in std_logic; RESETB :in std_logic ); end test_global; architecture TEST_GLOBAL_ARC of TEST_GLOBAL is ---------------------------------------------------------- -- Declaration des composants -- ---------------------------------------------------------- component COMMUTATEUR port ( CLK :in std_logic; RESETB :in std_logic; E_Cellule :in IOCELL; S_Cellule :out IOCELL; WRITEGENE :in std_logic_vector(15 downto 0); READCONSOM :in std_logic_vector(15 downto 0); WRENGENE :out std_logic_vector(15 downto 0); RDENCONSOM :out std_logic_vector(15 downto 0) ); end component; component CONSOMMATEUR port( READ :out std_logic_vector(15 downto 0); RDEN :in std_logic_vector(15 downto 0) ); end component; component GENE_CEL port ( WRITEGENE : out std_logic_vector(15 downto 0); WRENGENE : in std_logic_vector(15 downto 0); E_CELLULE : out std_logic_vector(63 downto 0) ); end component; ---------------- Signaux Internes ----------------------- signal In_cellule :IOCELL; signal S_Cellule :IOCELL; signal E_CELLULE : std_logic_vector(63 downto 0); signal WRITEGENE : std_logic_vector(15 downto 0); signal READCONSOM : std_logic_vector(15 downto 0); signal WRENGENE : std_logic_vector(15 downto 0); signal RDENCONSOM : std_logic_vector(15 downto 0); begin ------------------------------------------------------------ ------------- Instanciation du generateur de cellules ------ ------------------------------------------------------------ instancGENE_CEL :GENE_CEL port map( WRITEGENE => WRITEGENE, WRENGENE => WRENGENE, E_CELLULE => E_CELLULE ); ------------------------------------------------------------- ------------- Instanciation du commutateur ------------------ ------------------------------------------------------------- instancCOMMUT: COMMUTATEUR port map( CLK, RESETB, In_Cellule, S_Cellule, WRITEGENE, READCONSOM, WRENGENE, RDENCONSOM ); ------------------------------------------------------------- -------------- Instanciation du concommateur ---------------- ------------------------------------------------------------- instancConsom : CONSOMMATEUR port map( READ => READCONSOM, RDEN => RDENCONSOM ); process(CLK) -- Ce process permet de distribuer les cellules en entree vers -- l'entree de chaque commutateur. begin for i in 15 downto 0 loop In_CELLULE(i)<=E_cellule; end loop; end process; end Test_global_ARC;