----------------------------------------------------------------------------------
--  Antonio E COSTA						Jerome CAZIN	--
--				SEII3 - Decembre 96				--
--										--
--			Assemblage de l'entite commutateur 			--
--	Cette entite est composee de FIFO, CTRL_ENTREE et CTRL_SORTIES 		--
--		        compose de 16 Entrees/ 16 Sorties			--
----------------------------------------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

--library COMPASS_LIB;
--use COMPASS_LIB.COMPASS.ALL;
--use COMPASS_LIB.STDCOMP.all;
use WORK.UTIL.all;

-----------------------------------------------------------------------------------
--				Coeur du commutateur		      	      	 --
-----------------------------------------------------------------------------------

entity COMMUTATEUR is
	port (
		CLK		:in std_logic;
		RESETB		:in std_logic;
		E_Cellule 	:in IOCELL;
		S_Cellule	:out IOCELL;
		WRITEGENE	:in std_logic_vector(15 downto 0);
		READCONSOM	:in std_logic_vector(15 downto 0);
		WRENGENE	:out std_logic_vector(15 downto 0);
		RDENCONSOM	:out std_logic_vector(15 downto 0)
	      );
end COMMUTATEUR;

----------------------------------------------------------------------------------
--				Definition du coeur du commutateur	      	--
----------------------------------------------------------------------------------

architecture COMMUTATEUR_ARC of COMMUTATEUR is

-- Nombre de places dans les buffers d'entree --
constant NBENT :INTEGER :=1*7;

-- Nombre de places dans les buffers de sortie --
constant NBSORT:INTEGER :=16*7;

-- Declarartion des composants utilises --

 component FIFO
   generic(NB_BITS	:INTEGER;
	   NB_WORDS	:INTEGER
	  );

   port(   RAZ		: in std_logic;
	   CLK		: in std_logic;
	   WRITE	: in std_logic;
	   DI		: in std_logic_vector(NB_BITS downto 1);
	   READ		: in std_logic;
	   DO		: out std_logic_vector(NB_BITS downto 1);
	   RDEN		: out std_logic;
	   WREN		: out std_logic
	);
 end component;

 component CTRL_ENTREES
   port(   RESETB	:in std_logic;
	   CLK		:in std_logic;
	   RDEN		:in std_logic;
	   ENTREE_DONNEE:in std_logic_vector (63 downto 0);
	   SORTIE_DONNEE:out std_logic_vector(63 downto 0);
	   READ		:out std_logic_vector(15 downto 0);
	   VCI		:out std_logic_vector(15 downto 0);
	   prete	:out std_logic;
	   consom	:inout std_logic
	  
	);
 end component;

 component CTRL_SORTIES 
   port(  RESETB	:in std_logic;
	  CLK		:in std_logic;
	  SORTIE_DONNEE :in std_logic_vector(63 downto 0);
	  WREN		:in std_logic;
	  VCI		:in std_logic_vector(15 downto 0);
	  BUS_SORTIE	:out std_logic_vector (63 downto 0);
	  consom	:out std_logic;
	  WRITE		:out std_logic_vector(16 downto 1);
	  prete		:inout std_logic
	);
 end component;

-- Declaration des signaux internes servant a l'interconnection des composants --

 signal RDEN 	  	: std_logic;
 signal WREN 	  	: std_logic;
 signal PRETE		: std_logic;
 signal CONSOM		: std_logic;
 signal READ 	  	: std_logic_vector (15 downto 0);
 signal WRITE	  	: std_logic_vector (15 downto 0);
 signal VCI		: std_logic_vector (15 downto 0);
 signal BUS_SORTIE	: std_logic_vector (63 downto 0);
 SIGNAl ENTREE		: IOCELL;
 signal ENTREE_DONNEE 	: std_logic_vector (63 downto 0) bus;
 signal SORTIE_DONNEE	: std_logic_vector (63 downto 0);
 
begin 
-------- Instanciation des BUFFER d'entrée --------------------------------------

instancBUFFin : for I in 0 to 15 generate
 buff:FIFO
	generic map(NB_BITS => 64,NB_WORDS => NBENT)
	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITEGENE(I),
		  DI	=> E_Cellule(I),
		  READ  => READ (I),
		  DO	=> ENTREE_DONNEE,
		  RDEN	=> RDEN,
		  WREN	=> WRENGENE (I)
		 );
 end generate;

-------- Instanciation des BUFFER de sortie --------------------------------------

instancBUFFout : for I in 0 to 15 generate
 buff:FIFO
	generic map(NB_BITS => 64,NB_WORDS => NBSORT)
	port map (RAZ 	=> RESETB,
		  CLK	=> CLK,
		  WRITE => WRITE (I),
		  DI	=> BUS_SORTIE,
		  READ  => READCONSOM (I),
		  DO	=> S_Cellule(I),
		  RDEN	=> RDENCONSOM (I),
		  WREN	=> WREN
		 );
 end generate;

-------- Instanciation de Controle Entrée --------------------------------------

instancCTRL_ENTREES:CTRL_ENTREES
	port map (RESETB	=> RESETB,
		  CLK		=> CLK,
		  RDEN		=> RDEN,
		  ENTREE_DONNEE => ENTREE_DONNEE,
		  SORTIE_DONNEE	=> SORTIE_DONNEE,
		  READ		=> READ,
		  VCI		=> VCI,
		  PRETE		=> PRETE,
		  CONSOM	=> CONSOM
		);

-------- Instanciation de Controle Sorties --------------------------------------

instancCTRL_SORTIES:CTRL_SORTIES
	port map (RESETB	=> RESETB,
		  CLK		=> CLK,
		  SORTIE_DONNEE => SORTIE_DONNEE,
		  WREN		=> WREN,
		  VCI		=> VCI,
		  BUS_SORTIE	=> BUS_SORTIE,
		  CONSOM	=> CONSOM,
		  WRITE		=> WRITE,
		  PRETE		=> PRETE
		 );
		 
end COMMUTATEUR_ARC;




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