entity MEALY_MACHINE is
  port(clock,input: in BIT; output: inout BIT);
end MEALY_MACHINE;

architecture STATE_SEQUENCE of MEALY_MACHINE is
      type STATE is (state0,state1,state2);
      type RES_TYPE is array(INTEGER range <>) of STATE;

      function STATE_RES_FUNC(signal input: RES_TYPE) return STATE is
	variable resolved_value: STATE:=state0;
        begin
          for i in input'range loop
	    resolved_value:=input(i);
          end loop;
        return resolved_value;
      end STATE_RES_FUNC;
      subtype RES_STATE is STATE_RES_FUNC STATE;
      signal state_reg: RES_STATE register:=state0;
  begin
    S0: block(state_reg=state0 and clock='1' and not clock'stable )
      --disconnect state_reg: RES_STATE after 0 ns;
      begin
	state_reg <= guarded state1 when input='0'
		     else state2;
        end block S0;
    S1: block(state_reg=state1 and clock='1' and not clock'stable )
      --disconnect state_reg: RES_STATE after 0 ns;
      begin
	state_reg <= guarded state1 when input='0'
		     else state2;
        end block S1;
    S2: block(state_reg=state2 and clock='1' and not clock'stable )
      --disconnect state_reg: RES_STATE after 0 ns;
      begin
	state_reg <= guarded state1 when input='0'
		     else state2;
        end block S2;

-- output
  output <= '0' when state_reg=state0 else
	    '1' when state_reg=state1 and input='0' else
	    '0' when state_reg=state1 and input='1' else
	    '0' when state_reg=state2 and input='0' else
	    '1' when state_reg=state2 and input='1' else
	    output;
end STATE_SEQUENCE;
-- end of MEALY_MACHINE description

entity CLOCK is
generic(cycletime:POSITIVE);
port(phase0,phase1:out BIT);
end CLOCK;

architecture USINGATTRIB of CLOCK is
signal controlsignal:BIT:='0';
begin
  controlsignal<= not controlsignal after cycletime*1ns;
  phase0<= controlsignal;
  phase1<= controlsignal'delayed(cycletime*1ns/2);
end USINGATTRIB;

entity vMM is
end vMM;

architecture SIMPLE of vMM is
signal ph0,ph1:BIT;
signal i1,o1:BIT;
component CLOCK
generic(cycletime:POSITIVE);
port(phase0,phase1:out BIT);
end component;
component MM
  port(clock,input: in BIT; output: inout BIT);
end component;
for iCLK:CLOCK use entity work.CLOCK(USINGATTRIB);
for iMM:MM use entity work.MEALY_MACHINE(STATE_SEQUENCE);
begin
    iCLK:CLOCK
    generic map(10)
    port map(ph0,ph1);
    iMM:MM
    port map(ph1,i1,o1);
    process
      begin
	i1<= '1' , '0' after 20ns, '1' after 40ns,
	    '0' after 70ns, '1' after 80ns, '0' after 120ns,
	    '1' after 130ns, '0' after 180ns;
    end process;
end SIMPLE;


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