-- test of RAM
library syst;
use syst.TSL.all;
use syst.SYS.all;

entity vRAM is 
end vRAM;

architecture TEST of vRAM is
signal r,w,s:BIT;
signal d:WORD;
signal a:ADDR;
component RAM
  generic(rdel,disdel: POSITIVE);
  port(data:inout WORD;address:in ADDR;read,write,cs:BIT);
end component;
for iRAM:RAM use entity work.RAM(SIMPLE);
begin
iRAM:RAM generic map(20,10)
	 port map(d,a,r,w,s);
vP: process
  begin
  a<="00001","10000" after 30ns,"00001" after 50ns;

  d<="10101010","ZZZZZZZZ" after 40ns;
  w<='1' after 20ns,'0' after 30ns;
  s<='1' after 10ns,'0' after 40ns,'1' after 60ns,
     '0' after 100ns,'1' after 120ns,'0' after 150ns;
  r<='1' after 70ns, '0' after 90ns;
  wait;
  end process vP;
end TEST;


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