-- this entity tests ALU_stage entity
entity vALU is end vALU;
architecture SIMPLE of vALU is
signal s:BIT_VECTOR(3 downto 0);
signal a,b:BIT;
signal mode:BIT;
signal cin:BIT;
signal cout:BIT;
signal fun:BIT;
signal rc:BIT_VECTOR(7 downto 0);
component ALU_conf
  port(s3,s2,s1,s0,a1,b1,c1,m:BIT;c2,f1:out BIT);
end component;
component PRSIG_conf
generic(scale,size,width:POSITIVE);
port(gensig:out BIT_VECTOR(width-1 downto 0));
end component;
begin
  iALU:ALU_conf
       port map(s(3),s(2),s(1),s(0),a,b,cin,mode,cout,fun);
  iPRSIG:PRSIG_conf
	  generic map(1000,8,8)
	  port map(rc);
  s(3)<=rc(7);
  s(2)<=rc(6);
  s(1)<=rc(5);
  s(0)<=rc(4);
  a<=rc(3);
  b<=rc(2);
  cin<=rc(1);
  mode<=rc(0);

end SIMPLE;



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